Partial Reconfiguration Applied in an On-line Evolvable Pattern Recognition System

One of the main challenges with autonomous adaptable systems is the lack of hardware flexibility. However, reconfigurable logic is a promising technology for run-time adaptable systems ¿ often called reconfigurable computing. The paper outlines how reconfiguration can be applied at run-time for an o...

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Bibliographic Details
Published in:	2008 NORCHIP pp. 61 - 64
Main Authors:	Torresen, J., Senland, G.A., Glette, K.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-11-2008
Subjects:	Clocks Computer architecture Electronic mail Field programmable gate arrays Hardware Informatics Pattern recognition Reconfigurable logic Runtime Switches
Online Access:	Get full text
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Summary:	One of the main challenges with autonomous adaptable systems is the lack of hardware flexibility. However, reconfigurable logic is a promising technology for run-time adaptable systems ¿ often called reconfigurable computing. The paper outlines how reconfiguration can be applied at run-time for an on-line evolvable system to improve flexibility in the hardware. The challenge of the latter is to include flexibility without resynthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is presented in the paper. Results from implementation show that reconfiguration can be undertaken in a few milliseconds for one category detection module of our classification system.
ISBN:	1424424925 9781424424924
DOI:	10.1109/NORCHP.2008.4738283