Search Results - "Selfa, Vicent"
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Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance
Published in IEEE transactions on parallel and distributed systems (01-11-2020)“…The Last Level Cache (LLC) plays a key role in the system performance of current multi-cores by reducing the number of long latency main memory accesses. The…”
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Journal Article -
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Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology
Published in 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01-09-2017)“…Achieving system fairness is a major design concern in current multicore processors. Unfairness arises due to contention in the shared resources of the system,…”
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Conference Proceeding -
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A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches
Published in IEEE transactions on parallel and distributed systems (01-11-2017)“…Shared caches have become the common design choice in the vast majority of modern multi-core and many-core processors, since cache sharing improves throughput…”
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Journal Article -
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Efficient selective multicore prefetching under limited memory bandwidth
Published in Journal of parallel and distributed computing (01-10-2018)“…Current multicore systems implement multiple hardware prefetchers to tolerate long main memory latencies. However, memory bandwidth is a scarce shared resource…”
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Journal Article -
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A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies
Published in Journal of parallel and distributed computing (01-07-2017)“…The fast evolution of multicore processors makes it difficult for professors to offer computer architecture courses with updated contents. To deal with this…”
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Journal Article -
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Student research poster: A low complexity cache sharing mechanism to address system fairness
Published in 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT) (01-09-2016)“…Shared caches have become, de facto, the common design choice in current multi-cores, ranging from embedded devices to high-performance processors. In these…”
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Conference Proceeding -
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A Simple Activation/Deactivation Prefetching Scheme for Chip Multiprocessors
Published in 2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP) (01-02-2016)“…Prefetching significantly reduces the memory latencies of a wide range of applications and thus increases the system performance. However, as a speculative…”
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Conference Proceeding Journal Article -
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Methodologies and Performance Metrics to Evaluate Multiprogram Workloads
Published in 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (01-03-2015)“…Multicore processors are dominating the microprocessor market and most research work has moved to this kind of processors. Multicore research methods are still…”
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Conference Proceeding Journal Article -
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Row Tables: Design Choices to Exploit Bank Locality in Multiprogram Workloads
Published in 2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (01-03-2015)“…Main memory is a major performance bottleneck in current chip multiprocessors. Current DRAM banks latch the last accessed row in an internal buffer, namely row…”
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Conference Proceeding Journal Article -
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A Research-Oriented Course on Advanced Multicore Architecture
Published in 2015 IEEE International Parallel and Distributed Processing Symposium Workshop (01-05-2015)“…Multicore processors have become ubiquitous in our real life in devices like smartphones, tablets, etc. In fact, they are present in almost all segments of the…”
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Conference Proceeding