Search Results - "Sekhar, Vasarla Nagendra"

Heterogeneous System Level Integration Using Active Si Interposer by Chidambaram, Vivek, Lim Pei Siang, Sharon, Xiangyu, Wang, Sekhar, Vasarla Nagendra, Bhattacharya, Surya

“…Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA…”
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Panel Warpage of Fan-Out Panel-Level Packaging Using RDL-First Technology by Che, Fa Xing, Yamamoto, Kazunori, Rao, Vempati Srinivasa, Sekhar, Vasarla Nagendra

“…In this study, fan-out panel-level packaging (FO-PLP) technology using a redistribution layer (RDL) first approach is demonstrated using a large glass panel as…”
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Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects by Aibin Yu, Lau, J. H., Soon Wee Ho, Kumar, A., Wai Yin Hnin, Wen Sheng Lee, Ming Ching Jong, Sekhar, V. N., Kripesh, V., Pinjala, D., Chen, S., Chien-Feng Chan, Chun-Chieh Chao, Chi-Hsin Chiu, Chih-Ming Huang, Chen, C.

“…Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper…”
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Cu Damascene Process on Temporary Bonded Wafers for Thin Chip Stacking using Cu-Cu Hybrid Bonding by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Lianto, Prayudi, Chong, Ser Choong, Rao, Vempati Srinivasa

“…Hybrid bonding is one of the innovative permanent bonding technologies that form dielectric-dielectric and metal-metal bonds, respectively. Hybrid bonding is…”
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Study on the Effect of Wafer Back Grinding Process on Nanomechanical Behavior of Multilayered Low-k Stack by Sekhar, V. N., Lu Shen, Kumar, A., Tai Chong Chai, Xiaowu Zhang, Premchandran, C. S., Kripesh, V., Seung Wook Yoon, Lau, J. H.

“…This paper presents the effect of back grinding on the mechanical properties of the active side of the multilayered low-k stacked die. Low-k stacked wafers…”
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Process Challenges in Thin Wafers Fabrication with Double Side Hybrid Bond Pads for Chip Stacking by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Rao, B.S.S. Chandra, Choong Chong, Ser, Rao, Vempati Srinivasa

“…3D packaging with stacked dies is widely explored as a future advanced packaging technology for applications involving high-performance computing and High…”
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Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications by Sekhar, Vasarla Nagendra, Kumar, Mishra Dileep, Tippabhotla, Sasi Kumar, Rao, B. S. S. Chandra, Daniel, Ismael Cereno, Chong, Ser Choong, Rao, Vempati Srinivasa

“…The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings,…”
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Reliability Assessment of 2.5D Module using Chip to Wafer Hybrid Bonding by Chong, Ser Choong, Au Keng Yuen, Jason, Sekhar, Vasarla Nagendra, Cereno Daniel, Ismael, Kumar, Mishra Dileep, Srinivasa Rao, Vempati

“…Wafer to wafer hybrid bonding has been established to form fine pitch interconnections for high density I/O applications [1], [2]. However, this approach has…”
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Evaluation of Low Temperature Inorganic Dielectric Materials for Hybrid Bonding Applications by Kumar, Mishra Dileep, Nagendra Sekhar, Vasarla, Choong, Chong Ser, Chandra Rao, B.S.S., Chui, King-Jien, Rao, Vempati Srinivasa

“…High-bandwidth memory (HBM) market is witnessing huge demand for high performance computing. Vertical/3D stacking of memory chips using hybrid bonding is a…”
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Polymer Dielectric Materials Evaluation for Hybrid Bonding Applications by Sekhar, Vasarla Nagendra, Fujiwara, Takenori, Araki, Hitoshi, Shoji, Yu, Jukei, Masaya, Nomura, Kota, Kumar, Mishra Dileep, Ser Choong, Chong, Rao, Vempati Srinivasa

“…Hybrid bonding is an emerging technology for advanced packaging and heterogeneous integration. In this work, Cu/polymer-based hybrid bonding is being evaluated…”
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Design, assembly and reliability of large die and fine-pitch Cu/low- k flip chip package by Ong, Yue Ying, Ho, Soon Wee, Vaidyanathan, Kripesh, Sekhar, Vasarla Nagendra, Jong, Ming Chinq, Yak Long, Samuel Lim, Wen Sheng, Vincent Lee, Wai, Leong Ching, Rao, Vempati Srinivasa, Ong, Jimmy, Ong, Xuefen, Zhang, Xiaowu, Seung, Yoon Uk, Lau, John H., Lim, Yeow Kheng, Yeo, David, Chan, Kai Chong, Yanfeng, Zhang, Tan, Juan Boon, Sohn, Dong Kyun

“…This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump…”
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Development of 4 die stack module using Hybrid bonding approach by Chong, Ser Choong, Keng Yuen, Jason Au, Sekhar, Vasarla Nagendra, Daniel, Ismael Cereno, Rao, Vempati Srinivasa

“…Die stacking is commonly used in memory modules. Solder micro-bumps and through silicon via (TSVs) are common interconnects, and it may not viable or suitable…”
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Dielectric Stack Optimization for Die-level Warpage Reduction for Chip-to-Wafer Hybrid Bonding by Rao, B.S.S. Chandra, Kumar, Mishra Dileep, Sekhar, Vasarla Nagendra, Daniel, Ismael Cereno, Tippabhotla, Sasi Kumar, Chong, Ser Choong, C, Hemanth Kumar, Rao, Vempati Srinivasa

“…Chip-to-wafer hybrid bonding is a promising packaging technology for bumpless and high-density interconnection. However, this approach presents numerous…”
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Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material by Rao, V. S., Sekhar, V. N., Ho Soon Wee, Rajoo, R., Sharma, G., Lim Ying Ying, Damaruganath, P.

“…In this paper, we present the evaluation results of low cure temperature (less than 200°C) dielectric materials (LCTDMs) in terms of processability and…”
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Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages by Sharma, G, Rao, V S, Kumar, A, Lim Ying Ying, Khong Chee Houe, Lim, S, Sekhar, V N, Rajoo, R, Kripesh, V, Lau, J H

“…Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional…”
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Development of a Cu/Low- k Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications by Xiaowu Zhang, Lau, J H, Premachandran, C S, Ser-Choong Chong, Leong Ching Wai, Lee, V, Chai, T C, Kripesh, V, Sekhar, V N, Pinjala, D, Che, F X

“…Consumers' demands have driven the industry toward devices and packages with low cost, high performance, and multiple functions. Stacking two or more chips…”
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Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package by Yue Ying Ong, Soon Wee Ho, Sekhar, V N, Xuefen Ong, Ong, J, Xiaowu Zhang, Vaidyanathan, K, Seung Uk Yoon, Lau, J H, Lim Yeow Kheng, Yeo, D, Kai Chong Chan, Yanfeng Zhang, Juan Boon Tan, Dong Kyun Sohn

“…This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm 2 Cu/low-K flip chip packages (65 nm technology) with 150 μm…”
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RDL-1st Fan-Out Panel Level Packaging (FOPLP) for Heterogeneous and Economical Packaging by Sekhar, Vasarla Nagendra, Rao, Vempati Srinivasa, Che, F.X., Choong, Chong Ser, Yamamoto, Kazunori

“…Established RDL-1 st fan out panel level packaging (FOPLP) processes and modules for Gen 3 panel (550x650 mm) sizes. RDL-1 st package test vehicle (TV) has…”
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Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices by Chen, Bangtao, Sekhar, Vasarla Nagendra, Jin, Cheng, Lim, Ying Ying, Toh, Justin See, Fernando, Sanchitha, Sharma, Jaibir

“…Packaging of radio frequency (RF) microelectromechanical system (MEMS) devices requires a good electrical performance, and thus requires the parasitic effects…”
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Development of Package-on-Package Using Embedded Wafer-Level Package Approach by Ser Choongv Chong, Wee, David Ho Soon, Rao, Vempati Srinivasa, Vasarla, Nagendra Sekhar

“…The ever-increasing demands of higher performance, multiple functions, higher density, and lower cost mandate the reduction of the I/O pitch on the die as well…”
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