Search Results - "Seiculescu, Ciprian"

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips by Seiculescu, Ciprian, Murali, Srinivasan, Benini, Luca, De Micheli, Giovanni

“…Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the integration challenges faced by current systems on chips (SoCs)…”
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Efficient Unaligned Memory Access of Tightly Packed Weights for Deep Neural Network Inference on Edge Devices by Seiculescu, Ciprian

“…The increase in computational power enabled complex problems to be solved by employing new techniques from the field of Artificial Intelligence (AI) based on…”
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Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands by Seiculescu, Ciprian, Murali, Srinivasan, Benini, Luca, De Micheli, Giovanni

“…In many of today's system-on-chip (SoC) designs, the cores are partitioned into multiple voltage and frequency islands (VFIs), and the global interconnect is…”
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SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips by Seiculescu, C., Murali, S., Benini, L., De Micheli, G.

“…Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an…”
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A method to remove deadlocks in Networks-on-Chips with Wormhole flow control by Seiculescu, Ciprian, Murali, Srinivasan, Benini, Luca, De Micheli, Giovanni

“…Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is…”
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Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks by Orasan, Ioan Lucan, Seiculescu, Ciprian, Caleanu, Catalin Daniel

“…Deploying deep neural network models on the resource constrained devices, e.g., lost-cost microcontrollers, is challenging because they are mostly limited in…”
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3.5-D integration: A case study by Bobba, Shashikanth, Gaillardon, Pierre-Emmanuel, Seiculescu, Ciprian, Pavlidis, Vasilis F., De Micheli, Giovanni

“…Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred as 3-D TSV…”
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NoC topology synthesis for supporting shutdown of voltage islands in SoCs by Seiculescu, Ciprian, Murali, Srinivasan, Benini, Luca, De Micheli, Giovanni

“…In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce…”
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Proposal of Energy Independent Greenhouse by Ilies, Elisei, Marinca, Magdalena, Bularka, Szilard, Vajda, Melinda, Albulescu, Daiana, Seiculescu, Ciprian

“…This paper proposes an architecture of an energy independent and automated greenhouse. Energy independence is obtained by using Dye-sensitized Solar Cells…”
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Synthesis of networks on chips for 3D systems on chips by Murali, Srinivasan, Seiculescu, Ciprian, Benini, Luca, De Micheli, Giovanni

“…Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs)…”
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Synthesis of networks on chips for 3D systems on chips by Murali, S., Seiculescu, C., Benini, L., De Micheli, G.

“…Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs)…”
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CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers by Volos, S., Seiculescu, C., Grot, B., Pour, N. K., Falsafi, B., De Micheli, G.

“…Many core chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore's Law. In these…”
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A distributed interleaving scheme for efficient access to WideIO DRAM memory by Seiculescu, Ciprian, Benini, Luca, De Micheli, Giovanni

“…Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip…”
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A DRAM Centric NoC Architecture and Topology Design Approach by Seiculescu, C., Murali, S., Benini, L., De Micheli, G.

“…Most communication traffic in today's System on Chips (SoC) is DRAM centric. The NoC should be designed to efficiently handle the many-to-one communication…”
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A floorplan-aware interactive tool flow for NoC design and synthesis by Reza Kakoee, M., Angiolin, F., Murali, S., Pullini, A., Seiculescu, C., Benini, L.

“…In this paper we present a floorplan-aware toolchain for NoC design and synthesis integrated with a graphical front-end. The resulting design methodology is…”
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