Investigation of Mechanical Reliability of Cu/low-k Multi-layer Interconnects in Flip Chip Packages

The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-modeling approach was used to analyze the CPI to link the deformation from the package...

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Bibliographic Details
Published in:	2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007 pp. 1 - 5
Main Authors:	Uchibori, C.J., Xuefeng Zhang, Sehyuk Im, Ho, P.S., Nakamura, T.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-04-2007
Subjects:	Finite element methods Flip chip Integrated circuit interconnections Materials reliability Packaging Performance analysis Thermal stresses Ultra large scale integration Wafer scale integration Wiring
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Summary:	The impact of chip-package interaction (CPI) on the reliability of Cu/low-k interconnects in a flip-chip package for high performance ULSI was investigated using finite element analysis (FEA). A 3D four-level sub-modeling approach was used to analyze the CPI to link the deformation from the package level to the interconnect level. The energy release rate (ERR) and fracture mode at critical interface were calculated using a A modified virtual crack closure technique (MVCC). The simulation was focused on the die attach process for Pb- free process before underfilling where the maximum CPI effect is expected. First the general characteristics of CPI were analyzed for interfaces in two metal-layer interconnects. The ERR was found to increase rapidly with decreasing modulus of Inter Layer Dielectric (ILD) although the effect of CTE of ILD was found to be small. Next, the CPI for a four metal-layer structure was investigated. Here the ERR for upper M3 and M4 levels were consistently higher than those of lower Ml and M2 levels. If the same low-k ILD is used for all layers, the M4 interfaces show 2.5 times higher ERR than the lower levels. However, when TEOS is used in the M4 level, the ERR at M3 interfaces becomes 35% higher than the M4 level. The wiring dimensions and ILD properties were found to be important in controlling CPI. The CPI impact on ultra low-k reliability and interconnect design rules for the 65 nm technology and beyond are discussed.
ISBN:	142441105X 9781424411054
DOI:	10.1109/ESIME.2007.360022