Search Results - "See, G.H."

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  1. 1

    Physics-based single-piece charge model for strained-Si MOSFETs by Chandrasekaran, K., Xing Zhou, Chiah, S.B., Shangguan, W., Guan Huei See

    Published in IEEE transactions on electron devices (01-07-2005)
    “…A physics-based single-piece charge model for strained-silicon (s-Si) MOSFETs from accumulation to strong-inversion regions is presented. The model is…”
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    Journal Article
  2. 2

    A compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source/drain by Zhu, G.J., Zhou, X., Lee, T.S., Ang, L.K., See, G.H., Lin, S.H.

    “…A physics-based compact model for undoped symmetric double-gate MOSFETs with Schottky-barrier source and drain is formulated based on the quasi-2D…”
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    Conference Proceeding
  3. 3

    Physics based scalable MOSFET mismatch model for statistical circuit simulation by Lim, G.H., Zhou, X., Khu, K., Yoo, Y.K., Poh, F., See, G.H., Zhu, Z.M., Wei, C.Q., Lin, S.H., Zhu, G.J.

    “…MOSFET mismatch model based on BSIM3v3 for a CMOS 0.13 μm technology using backward propagation of variance (BPV) methodology coupled with Pelgrom model basis…”
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    Conference Proceeding
  4. 4

    A rigorous surface-potential-based I-V model for undoped cylindrical nanowire MOSFETs by Lin, S.H., Zhou, X., See, G.H., Zhu, Z.M., Lim, G.H., Wei, C.Q., Zhu, G.J., Yao, Z.H., Wang, X.F., Yee, M., Zhao, L.N., Hou, Z.F., Ang, L.K., Lee, T.S., Chandra, W.

    “…A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is…”
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    Conference Proceeding
  5. 5

    New challenges in MOS compact modeling for future generation CMOS by Zhou, X., See, G.H., Zhu, G.J., Zhu, Z.M., Lin, S.H., Wei, C.Q., Srinivas, A., Zhang, J.B.

    “…As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as…”
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    Conference Proceeding
  6. 6

    Impact of BEOL, multi-fingered layout design, and gate protection diode on intrinsic MOSFET threshold voltage mismatch by Lim, G.H., Zhou, X., Khu, K., Yoo, Y.K., Poh, F., See, G.H., Zhu, Z.M., Wei, C.Q., Lin, S.H., Zhu, G.J.

    “…Continued scaling down of MOSFETs, compounded with limitation in process variation control capabilities, has made MOSFET mismatch more significant for advanced…”
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    Conference Proceeding