Search Results - "Scheuermann, Michael"

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling by Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm…”
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Redox-Responsive Protein Design: Design of a Small Protein Motif Dependent on Glutathionylation by Scheuermann, Michael J, Forbes, Christina R, Zondlo, Neal J

“…Cysteine S-glutathionylation is a protein post-translational modification that promotes cellular responses to changes in oxidative conditions. The design of…”
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Arginine Mimetics Using α-Guanidino Acids: Introduction of Functional Groups and Stereochemistry Adjacent to Recognition Guanidiniums in Peptides by Balakrishnan, Shalini, Scheuermann, Michael J., Zondlo, Neal J.

“…Arginine residues are broadly employed for specific biomolecular recognition, including in protein–protein, protein–DNA, and protein–RNA interactions. Arginine…”
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Analysis and Modeling of DC Current Crowding for TSV-Based 3-D Connections and Power Integrity by Xin Zhao, Scheuermann, Michael R., Sung Kyu Lim

“…3-D integration using through-silicon-vias (TSVs) is emerging as one of the key technology options for continued miniaturization. However, because of increased…”
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A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias by Wordeman, M., Silberman, J., Maier, G., Scheuermann, M.

“…3D integration (3DI) holds promise for improved performance of integrated systems by increasing interconnect bandwidth [1]. A processor stacked with cache…”
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Efficient AI System Design With Cross-Layer Approximate Computing by Venkataramani, Swagath, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Choi, Jungwook, Kang, Mingu, Agarwal, Ankur, Oh, Jinwook, Jain, Shubham, Babinsky, Tina, Cao, Nianzheng, Fox, Thomas, Fleischer, Bruce, Gristede, George, Guillorn, Michael, Haynie, Howard, Inoue, Hiroshi, Ishizaki, Kazuaki, Klaiber, Michael, Lo, Shih-Hsien, Maier, Gary, Mueller, Silvia, Scheuermann, Michael, Ogawa, Eri, Schaal, Marcel, Serrano, Mauricio, Silberman, Joel, Vezyrtzis, Christos, Wang, Wei, Yee, Fanchieh, Zhang, Jintao, Ziegler, Matthew, Zhou, Ching, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Srinivasan, Vijayalakshmi, Chang, Leland, Gopalakrishnan, Kailash

“…Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered…”
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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference by Venkataramani, Swagath, Srinivasan, Vijayalakshmi, Wang, Wei, Sen, Sanchari, Zhang, Jintao, Agrawal, Ankur, Kar, Monodeep, Jain, Shubham, Mannari, Alberto, Tran, Hoang, Li, Yulong, Ogawa, Eri, Ishizaki, Kazuaki, Inoue, Hiroshi, Schaal, Marcel, Serrano, Mauricio, Choi, Jungwook, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Allain, Allison, Bonano, James, Cao, Nianzheng, Casatuta, Robert, Cohen, Matthew, Fleischer, Bruce, Guillorn, Michael, Haynie, Howard, Jung, Jinwook, Kang, Mingu, Kim, Kyu-hyoun, Koswatta, Siyu, Lee, Saekyu, Lutz, Martin, Mueller, Silvia, Oh, Jinwook, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Schelm, Kerstin, Scheuermann, Michael, Silberman, Joel, Yang, Jie, Zalani, Vidhi, Zhang, Xin, Zhou, Ching, Ziegler, Matt, Shah, Vinay, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their…”
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Arginine Mimetics via α-Guanidino Acids: Introduction of Functional Groups and Stereochemistry Adjacent to Recognition Guanidiniums in Peptides by Balakrishnan, Shalini, Scheuermann, Michael J., Zondlo, Neal J.

“…Arginine residues are broadly employed for specific biomolecular recognition, including in protein-protein, protein-DNA, and protein-RNA interactions. Arginine…”
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A Scalable Multi-TeraOPS Core for AI Training and Inference by Shukla, Sunil, Fleischer, Bruce, Ziegler, Matthew, Silberman, Joel, Oh, Jinwook, Srinivasan, Vijayalakshmi, Choi, Jungwook, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Cao, Nianzheng, Chen, Chia-Yu, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Lee, Dongsoo, Lo, Shih-Hsien, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Lu, Pong-Fei, Curran, Brian, Chang, Leland, Gopalakrishnan, Kailash

“…This letter presents a multi-TOPS AI accelerator core for deep learning training and inference. With a programmable architecture and custom ISA, this engine…”
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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling by Agrawal, Ankur, Lee, Sae Kyu, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia, Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kar, Monodeep, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael, Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…Low-precision computation is the key enabling factor to achieve high compute densities (TOPS/W and TOPS/mm 2 ) in AI hardware accelerators across cloud and…”
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A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference by Fleischer, Bruce, Shukla, Sunil, Ziegler, Matthew, Silberman, Joel, Jinwook Oh, Srinivasan, Vijavalakshmi, Jungwook Choi, Mueller, Silvia, Agrawal, Ankur, Babinsky, Tina, Nianzheng Cao, Chia-Yu Chen, Chuang, Pierce, Fox, Thomas, Gristede, George, Guillorn, Michael, Haynie, Howard, Klaiber, Michael, Dongsoo Lee, Shih-Hsien Lo, Maier, Gary, Scheuermann, Michael, Venkataramani, Swagath, Vezyrtzis, Christos, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Curran, Brian, Lel Chang, Gopalakrishnan, Kailash

“…A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers. With a programmable…”
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Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs by Zhao, Xin, Scheuermann, Michael, Lim, Sung Kyu

“…Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works…”
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Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETs by Dubois, E., Shahidi, G.G., Scheuermann, M.R.

“…An anomalous output voltage overshoot observed during the turn-off of single short-channel thin-film silicon-on-insulator SOI n-MOSFETs is reported. The…”
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Design and Modeling Methodology of Vertical Interconnects for 3DI Applications : THROUGH SILICON VIAS by GORDIN, Rachel, GOREN, David, SHLAFMAN, Shlomo, ELAD, Danny, SCHEUERMANN, Michael, YOUNG, Albert, FEI LIU, XIAOXIONG GU, TYBERG, Christy

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Design and Modeling Methodology of Vertical Interconnects for 3DI Applications by Gordin, R, Goren, D, Shlafman, S, Elad, D, Scheuermann, M, Young, A, Fei Liu, Xiaoxiong Gu, Tyberg, C

“…This paper presents a design and modeling methodology of vertical interconnects for three-dimensional integration (3DI) applications. Compact semi-analytical…”
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A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference by Oh, Jinwook, Lee, Sae Kyu, Kang, Mingu, Ziegler, Matthew, Silberman, Joel, Agrawal, Ankur, Venkataramani, Swagath, Fleischer, Bruce, Guillorn, Michael, Choi, Jungwook, Wang, Wei, Mueller, Silvia, Ben-Yehuda, Shimon, Bonanno, James, Cao, Nianzheng, Casatuta, Robert, Chen, Chia-Yu, Cohen, Matt, Erez, Ophir, Fox, Thomas, Gristede, George, Haynie, Howard, Ivanov, Vicktoria, Koswatta, Siyu, Lo, Shih-Hsien, Lutz, Martin, Maier, Gary, Mesh, Alex, Nustov, Yevgeny, Rider, Scot, Schaal, Marcel, Scheuermann, Michael, Sun, Xiao, Wang, Naigang, Yee, Fanchieh, Zhou, Ching, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…A processor core is presented for AI training and inference products. Leading-edge compute efficiency is achieved for robust fp16 training via efficient…”
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Decoupling capacitor modeling and characterization for power supply noise in 3D systems by Zheng Xu, Putnam, C., Xiaoxiong Gu, Scheuermann, M., Rose, K., Webb, B., Knickerbocker, J., Jian-Qiang Lu

“…Decoupling capacitors are essential to reduce high transient current noise and to provide a low impedance power delivery path. 3D technology has several…”
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Design, CAD and technology challenges for future processors: 3D perspectives by Burns, Jeff, Carpenter, Gary, Kursun, Eren, Puri, Ruchir, Warnock, James, Scheuermann, Michael

“…Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This…”
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Physical design of a fourth-generation POWER GHz microprocessor by Anderson, C.J., Petrovick, J., Keaty, J.M., Warnock, J., Nussbaum, G., Tendier, J.M., Carter, C., Chu, S., Clabes, J., DiLullo, J., Dudley, P., Harvey, P., Krauter, B., LeBlanc, J., Pong-Fei Lu, McCredie, B., Plum, G., Restle, P.J., Runyon, S., Scheuermann, M., Schmidt, S., Wagoner, J., Weiss, R., Weitzel, S., Zoric, B.

“…The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all…”
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Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs by Xin Zhao, Yang Wan, Scheuermann, Michael, Sung Kyu Lim

“…In this paper, we present a transient modeling of electromigration (EM) in TSV and TSV-to-wire interfaces in the power delivery network (PDN) of 3D ICs. In…”
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