On Automating FPGA Design Build Flow Using GitLab CI

On Automating FPGA Design Build Flow Using GitLab CI

Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programm...

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Bibliographic Details
Published in:IEEE embedded systems letters Vol. 16; no. 2; pp. 227 - 230
Main Authors: Eguzo, Chimezie, Scherer, Benedikt, Kebel, Daniel, Bekman, Ilja, Streun, Matthias, Schlosser, Mario, van Waasen, Stefan
Format: Journal Article
Language:English
Published: Piscataway IEEE 01-06-2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Automation
Computer architecture
continuous integration and continuous deployment (CI/CD)
cross-compilation
embedded Linux
Embedded systems
field programmable gate array (FPGA)
Field programmable gate arrays
Hardware
PetaLinux
Pipelines
Positron emission
Positron emission tomography
Project development
Queueing
Software
software development
System on chip
Testing
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Description
Summary:Building and testing software for embedded systems can be challenging with an impact on delivery time, design reproducibility, and collaboration among project contributors. To accelerate project development, presented here is an automated build flow that utilizes Xilinx PetaLinux, and field programmable gate array (FPGA) hardware description and integrates with the GitLab continuous integration and continuous deployment (CI/CD) framework for embedded targets. This build flow automates the complete process of FPGA implementation, PetaLinux configuration, and cross-compilation of software essentials for the target system-on-chip (SoC). The system has been successfully deployed in cross-compiling the control and command toolset for the Positron Emission Tomography scanner (PhenoPET) and the implementation of the message queuing telemetry transport (MQTT) service on a Xilinx Zynq Ultrascale MPSoC. This approach can be easily adapted to other projects with specific requirements.
ISSN:1943-0663
1943-0671
DOI:10.1109/LES.2023.3314148