Search Results - "Schelm, Kerstin"

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling by Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm…”
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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference by Venkataramani, Swagath, Srinivasan, Vijayalakshmi, Wang, Wei, Sen, Sanchari, Zhang, Jintao, Agrawal, Ankur, Kar, Monodeep, Jain, Shubham, Mannari, Alberto, Tran, Hoang, Li, Yulong, Ogawa, Eri, Ishizaki, Kazuaki, Inoue, Hiroshi, Schaal, Marcel, Serrano, Mauricio, Choi, Jungwook, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Allain, Allison, Bonano, James, Cao, Nianzheng, Casatuta, Robert, Cohen, Matthew, Fleischer, Bruce, Guillorn, Michael, Haynie, Howard, Jung, Jinwook, Kang, Mingu, Kim, Kyu-hyoun, Koswatta, Siyu, Lee, Saekyu, Lutz, Martin, Mueller, Silvia, Oh, Jinwook, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Schelm, Kerstin, Scheuermann, Michael, Silberman, Joel, Yang, Jie, Zalani, Vidhi, Zhang, Xin, Zhou, Ching, Ziegler, Matt, Shah, Vinay, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their…”
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SIMD Multi Format Floating-Point Unit on the IBM z15(TM) by Payer, Stefan, Lichtenau, Cedric, Klein, Michael, Schelm, Kerstin, Leber, Petra, Hofmann, Nicol, Babinsky, Tina

“…The IBM z Systems(TM) is the backbone of the insurance, banking, and retail industry. Innovation in these markets is driving the demand for new and additional…”
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9.1 A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling by Agrawal, Ankur, Lee, Sae Kyu, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia, Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kar, Monodeep, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael, Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Chang, Leland, Gopalakrishnan, Kailash

“…Low-precision computation is the key enabling factor to achieve high compute densities (TOPS/W and TOPS/mm 2 ) in AI hardware accelerators across cloud and…”
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The POWER7 Binary Floating-Point Unit by Boersma, M., Kroner, M., Layer, C., Leber, P., Muller, S. M., Schelm, K.

“…The binary Floating-Point Unit (FPU) of the POWER7 processor is a 5.5 cycle Fused Multiply-Add (FMA) design, fully compliant with the IEEE 754-2008 standard…”
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