Search Results - "Sassman, Barry"

Plasma-Induced Damage in High- k/Metal Gate Stack Dry Etch by Hussain, M.M., Seung-Chul Song, Barnett, J., Chang Yong Kang, Gebara, G., Sassman, B., Moumen, N.

“…Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry…”
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High mobility CMOS transistors on Si/SiGe heterostructure channels by Oh, Jungwoo, Jeon, Kanghoon, Lee, Se-Hoon, Huang, Jeff, Hung, P.Y., Ok, Injo, Sassman, Barry, Ko, Dae-Hong, Kirsch, Paul, Jammy, Raj

“…We have demonstrated high mobility CMOS transistors on Si/SiGe heterostructure channels selectively grown on a Si (100) substrate. Electron and hole mobility…”
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Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors by Oh, Jungwoo, Huang, Jeff, Chen, Yen-Ting, Ok, Injo, Jeon, Kanghoon, Lee, Se-Hoon, Sassman, Barry, Loh, Wei-Yip, Lee, Hi-Deok, Ko, Dea-Hong, Majhi, Prashant, Kirsch, Paul, Jammy, Raj

“…We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal–oxide–semiconductor field-effect transistor). The poor…”
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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-[Formula Omitted]/Metal Gate by Lee, Se-Hoon, Majhi, Prashant, Ferrer, Domingo A, Hung, Pui-Yee, Huang, Jeff, Oh, Jungwoo, Loh, Wei-Yip, Sassman, Barry, Min, Byoung-Gi, Tseng, Hsing-Huang, Harris, Rusty, Bersuker, Gennadi, Kirsch, Paul D, Jammy, Raj, Banerjee, Sanjay K

“…Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels…”
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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-κ/Metal Gate by LEE, Se-Hoon, MAJHI, Prashant, HARRIS, Rusty, BERSUKER, Gennadi, KIRSCH, Paul D, JAMMY, Raj, BANERJEE, Sanjay K, FERRER, Domingo A, HUNG, Pui-Yee, HUANG, Jeff, OH, Jungwoo, LOH, Wei-Yip, SASSMAN, Barry, MIN, Byoung-Gi, TSENG, Hsing-Huang

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Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate by Se-Hoon Lee, Majhi, P., Ferrer, D. A., Pui-Yee Hung, Huang, J., Oh, J., Wei-Yip Loh, Sassman, B., Byoung-Gi Min, Hsing-Huang Tseng, Harris, R., Bersuker, G., Kirsch, P. D., Jammy, R., Banerjee, S. K.

“…Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels…”
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Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation by Wei-Yip Loh, Etienne, H., Coss, B., Ok, I., Turnbaugh, D., Spiegel, Y., Torregrosa, F., Banti, J., Roux, L., Pui-Yee Hung, Jungwoo Oh, Sassman, B., Radar, K., Majhi, P., Hsing-Huang Tseng, Jammy, R.

“…Using a presilicide implantation approach, we demonstrate that the Schottky barrier height (SBH) of NiSi/n-Si(100) can be modulated by doping a Si substrate…”
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Deposition thickness based high-throughput nano-imprint template by Hussain, Muhammad Mustafa, Labelle, Ed, Sassman, Barry, Gebara, Gabe, Lanee, Sidi, Moumen, Naim, Larson, Larry

“…International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low…”
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Demonstration of L \sim \hbox\ \hbox pMOSFETs With \hbox\hbox/\hbox Channels, High I/I\ (≫ \hbox \times \hbox^) , and Controlled Short Channel Effects (SCEs) by Se-Hoon Lee, Majhi, P., Jungwoo Oh, Sassman, B., Young, C., Bowonder, A., Wei-Yip Loh, Kyu-Jin Choi, Byung-Jin Cho, Hi-Deok Lee, Kirsch, P., Harris, H.R., Tsai, W., Datta, S., Hsing-Huang Tseng, Banerjee, S.K., Jammy, R.

“…High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first…”
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Demonstration of Lg ∼ 55 nm pMOSFETs With Si/Si0.25Ge0.75/Si Channels, High Ion /Ioff (> 5 x 104), and Controlled Short Channel Effects (SCEs) by LEE, Se-Hoon, MAJHI, Prashant, KIRSCH, Paul, HARRIS, Harlan R, TSAI, Wilman, DATTA, Suman, TSENG, Hsing-Huang, BANERJEE, Sanjay K, JAMMY, Raj, OH, Jungwoo, SASSMAN, Barry, YOUNG, Chadwin, BOWONDER, Anupama, LOH, Wei-Yip, CHOI, Kyu-Jin, CHO, Byung-Jin, LEE, Hi-Deok

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CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction by Coss, Brian E., Loh, Wei-Yip, Oh, Jungwoo, Smith, Greg, Smith, Casey, Adhikari, Hemant, Sassman, Barry, Parthasarathy, Srivatsan, Barnett, Joel, Majhi, Prashant, Wallace, Robert M., Kim, Jiyoung, Jammy, Raj

“…We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the…”
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Single Metal Gate with Dual Work Functions for FD-SOI and UTB Double Gate Technologies by Pham, Daniel, Luan, Hongfa, Mathur, Kaveri, Sassman, Barry, Nguyen, Billy, Brown, George, Yang, Ji-woon, Oh, Jungwoo, Zeitzoff, Peter, Larson, Larry

“…In this paper, we demonstrate an integratable single metal gate (TiSiN) on Hf x Si x O y with dual work functions (4.44eV and 4.83eV), achieved by varying the…”
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Dual work function high-k/Metal Gate CMOS FinFETs by Hussain, M.M., Smith, C., Kalra, P., Ji-Woon Yang, Gebara, G., Sassman, B., Kirsch, P., Majhi, P., Seung-Chul Song, Harris, R., Hsing-Huang Tseng, Jammy, R.

“…For the first time, a set of complementary metal oxide semiconductor (CMOS) FinFET devices with two different high-k/metal gate stacks of dual work function…”
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A novel technique to calculate the critical temperature of thermal agglomerations on patterned SOI wafers by Widodo, L., Pham, D., Sassman, B., Larson, L.

“…Thermal agglomeration of ultra-thin SOI (<20nm) is an undesirable issue for device fabrication. In this article for the first time, a methodology to calculate…”
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