Search Results - "Sass, Ron"

HwPMI : An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs by Sass, Ron, French, Matthew, Steiner, Neil, Schmidt, Andrew G.

“…Designing hardware cores for FPGAs can quickly become a complicated task, difficult even for experienced engineers. With the addition of more sophisticated…”
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Redsharc : A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip by Kritikos, William V., Schmidt, Andrew G., Sass, Ron, Anderson, Erik K., French, Matthew

“…The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the…”
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An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing by Schmidt, Andrew G., Kritikos, William V., Gao, Shanyuan, Sass, Ron

“…As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research…”
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Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10) by Feregrino, Claudia, Arias-Estrada, Miguel, Gaj, Kris, Prasanna, Viktor K., Santambrogio, Marco D., Sass, Ron

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A Hardware Filesystem Implementation with Multidisk Support by Mendon, Ashwin A., Schmidt, Andrew G., Sass, Ron

“…Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which…”
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A hardware–software co-design approach for implementing sparse matrix vector multiplication on FPGAs by Jain-Mendon, Shweta, Sass, Ron

“…The Field-Programmable Gate Array is an excellent match for the Sparse Matrix–Vector Multiply (SMVM) operation because of its enormous computational capacity…”
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Architecture and applications for an All-FPGA parallel computer by Rajasekhar, Yamuna, Sass, Ron

“…The Reconfigurable Computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices…”
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Analysis of a prototype intelligent network interface by Underwood, Keith D., Ligon III, Walter B., Sass, Ron R.

“…With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies…”
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Architecture and applications for an All-FPGA parallel computer : Unconventional Cluster Architectures and Applications by RAJASEKHAR, Yamuna, SASS, Ron

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An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster by Underwood, Keith D., Ligon III, Walter B., Sass, Ron R.

“…With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies…”
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A case study of streaming storage format for sparse matrices by Jain-Mendon, S., Sass, R.

“…The Field-Programmable Gate Array is an excellent match for the sparse matrix-vector multiply operation because of its enormous computational capacity and its…”
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Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster by Schmidt, Andrew G., Datta, Siddhartha, Mendon, Ashwin A., Sass, Ron

“…► Linear scaling achieved with two network topologies (up to 32×) on 32 nodes. ► Up to 512 parallel BLAST hardware cores implemented. ► Successful integration…”
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Design of a scalable digital Wireless Channel Emulator for networking radios by Buscemi, S., Sass, R.

“…The utilization of digital Wireless Channel Emulators (WCE) with networking radios is hampered by the inability to efficiently scale a digital WCE to a large…”
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Harnessing Unreliable Cores in Heterogeneous Architecture: The PyDac Programming Model and Runtime by Bin Huang, Sass, Ron, Debardeleben, Nathan, Blanchard, Sean

“…Heterogeneous many-core architectures combined with scratch-pad memories are attractive because they promise better energy efficiency than conventional…”
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Achieving Programming Model Abstractions for Reconfigurable Computing by Andrews, D., Sass, R., Anderson, E., Agron, J., Peck, W., Stevens, J., Baijot, F., Komp, E.

“…This paper introduces hthreads, a unifying programming model for specifying application threads running within a hybrid computer processing unit…”
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Iridescence and its applications in thin-film conformal uniformity by Smith, Krista L., Alisafaee, Hossein, Chaofan Wang, Sass, Ron, Tsinghua Her

“…Iridescence is structural color, as opposed to pigment, in which the color is a result of constructive or destructive interference of light traveling through…”
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Architecture and Applications for an All-FPGA Parallel Computer by Rajasekhar, Y., Sass, R.

“…The Reconfigurable Computing Cluster (RCC) project has been investigating unconventional architectures for high end computing using a cluster of FPGA devices…”
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Building problem-solving environments with the Arches framework by DeBardeleben, Nathan, Sass, Ron, Stanzione, Daniel, Ligon, Walter B.

“…The computational problems that scientists face are rapidly escalating in size and scope. Moreover, the computer systems used to solve these problems are…”
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Achieving Programming Model Abstractions for Reconfigurable Computing : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATION by ANDREWS, David, SASS, Ron, ANDERSON, Erik, AGRON, Jason, PECK, Wesley, STEVENS, Jim, BAIJOT, Fabrice, KOMP, Ed

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A Message from the General Chair and Program Chair

“…Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the…”
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