Search Results - "Sankman, Robert"

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  1. 1
    A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications

    A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications by Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Wang, Tao, Vangal, Sriram, Tschanz, James W., De, Vivek

    Published in IEEE journal of solid-state circuits (01-04-2017)
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  2. 2
    A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications

    A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications by Paul, Somnath, Honkote, Vinayak, Kim, Ryan Gary, Majumder, Turbo, Aseron, Paolo A., Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Tao Wang, Vangal, Sriram, Tschanz, James W., De, Vivek

    Published in IEEE journal of solid-state circuits (01-04-2017)
    “…An energy-harvesting wireless sensor node (WSN) integrates a 14-nm, 0.79-mm 2 , 32-b Intel Architecture corebased near-threshold voltage (NTV) microcontroller…”
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  3. 3
    Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect

    Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect by Mahajan, Ravi, Sankman, Robert, Patel, Neha, Dae-Woo Kim, Aygun, Kemal, Zhiguo Qian, Mekonnen, Yidnekachew, Salama, Islam, Sharan, Sujit, Iyengar, Deepti, Mallik, Debendra

    “…The EMIB dense MCP technology is a new packaging paradigm that provides localized high density interconnects between two or more die on an organic package…”
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  4. 4
    High performance package designs for a 1 GHz microprocessor

    High performance package designs for a 1 GHz microprocessor by Hasan, A., Sarangi, A., Baldwin, C.S., Sankman, R.L., Taylor, G.F.

    Published in IEEE transactions on advanced packaging (01-11-2001)
    “…This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor…”
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  5. 5
    An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS

    An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS by Paul, Somnath, Honkote, Vinayak, Kim, Ryan, Majumder, Turbo, Aseron, Paolo, Grossnickle, Vaughn, Sankman, Robert, Mallik, Debendra, Jain, Sandeep, Vangal, Sriram, Tschanz, James, De, Vivek

    “…A wireless sensor node (WSN) integrates a 0.79mm 2 near-threshold voltage (NTV) 32-bit Intel Architecture (IA) microcontroller (MCU) in 14nm tri-gate CMOS,…”
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  6. 6
    Low cost flip chip package design concepts for high density I/O

    Low cost flip chip package design concepts for high density I/O by Tee-Onn Chong, Seng-Hooi Ong, Teong-Guan Yew, Chee-Yee Chung, Sankman, R.

    “…The semiconductor industry at large is migrating from wire bond packaging to flip chip packaging due to electrical performance requirements. With the removal…”
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  7. 7
    Degradation measurements using fully processed test transistors in high density plasma reactors for failure analysis

    Degradation measurements using fully processed test transistors in high density plasma reactors for failure analysis by Muniandy, Ravisangar, Boylan, Ron, Chin, Roland, Bell, Nick, Sankman, Robert

    “…The objective of this study was for it to serve as a guide for understanding high density plasma induced damage during wafer fabrication and etchback for…”
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  8. 8
    High performance package designs for a 1 GHz microprocessor

    High performance package designs for a 1 GHz microprocessor by Hasan, A., Sarangi, A., Baldwin, C.S., Sankman, R.L., Taylor, G.F.

    “…This paper describes the architecture and design of an Organic Land Grid Array (OLGA) and a Flip Chip Pin Grid Array (FCPGA) package for a 32 bit…”
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    Conference Proceeding
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