A low-power deblocking filter architecture for H.264 advanced video coding

In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking filter process up to 208 clock cycles per 16x16 macroblock. The processing order of the filter is optimized to reduce power consumption...

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Bibliographic Details
Published in:	2007 IFIP International Conference on Very Large Scale Integration pp. 190 - 193
Main Authors:	Jaemoon Kim, Sangkown Na, Chong-Min Kyung
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-10-2007
Subjects:	Automatic voltage control Clocks Energy consumption Filtering Frequency Hardware Libraries Power filters Registers Video coding
Online Access:	Get full text
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Summary:	In this paper, a low-power deblocking filter architecture for H.264/AVC is proposed. A hybrid filtering order has been adopted to boost the speed of the deblocking filter process up to 208 clock cycles per 16x16 macroblock. The processing order of the filter is optimized to reduce power consumption and filter size and this is done by reducing memory access and raising the reusability of register blocks. A hardware implementation, under Samsung 0.18 μm standard cell library, consumes 18.34K gates at a clock frequency of 125MHz. Comparing to some state- of-the-art designs, the proposed architecture delivers the lowest level of power consumption while achieving similar speed of performance.
ISBN:	9781424417094 1424417090
ISSN:	2324-8432
DOI:	10.1109/VLSISOC.2007.4402496