Search Results - "Sang Won Son"
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A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
Published in IEEE journal of solid-state circuits (01-12-2021)“…This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula>…”
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A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
Published in IEEE journal of solid-state circuits (01-12-2017)“…A digital fractional-N phase-locked loop (PLL) is presented. It achieves 137and 142-fs rms jitter integrating from 10 kHz to 10 MHz and from 1 kHz to 10 MHz,…”
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Frequency-domain equalization for distributed terrestrial DTV transmission environments
Published in IEEE transactions on consumer electronics (01-02-2006)“…The 8-VSB modulation, the transmission standard for the terrestrial digital television (DTV) of the Advanced Television Systems Committee (ATSC), suffers from…”
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A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS
Published in IEEE journal of solid-state circuits (01-05-2016)“…We present a highly configurable, low-power, low-area, low-EVM, SAW-less transmitter (TX) architecture that is based on a dynamically biased power mixer. All…”
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Oculocardiac reflex during the endoscopic sinus surgery
Published in American journal of otolaryngology (01-03-2010)“…Abstract The oculocardiac reflex is developed by surgical or nonsurgical stimulations to the eyeball including manipulation of extraocular muscles. The authors…”
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A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM
Published in 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (01-06-2018)“…We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high…”
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Conference Proceeding -
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A dynamically-biased 2G/3G/4G multi-band transmitter with > 4dBm Pout, < −65dBc CIM3 and < −157dBc/Hz out-of-band noise in 28nm CMOS
Published in 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (01-05-2015)“…We present a highly-configurable, low-power, low-area, SAW-less TX architecture that is based on a dynamically-biased power mixer. All FDD/TDD bands for 4G LTE…”
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Conference Proceeding -
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The Effect of DizzyFIX in the Treatment of Benign Paroxysmal Positional Vertigo
Published in Otolaryngology-head and neck surgery (01-08-2011)“…Objective: The treatment of benign paroxysmal positional vertigo (BPPV) is a repositioning maneuver in order to remove otolithic debris. We use a new device…”
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만성 신부전에서 심폐 부전이 동반된 고마그네슘혈증
Published in Kidney research and clinical practice (30-03-2008)“…A 46-year-old woman with chronic renal failure due to polyarteritis nodosa was referred to the hospital for evaluation of abdominal pain. She had been treated…”
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단백질 C와 S 결핍에 의한 급성 신경색
Published in Kidney research and clinical practice (30-05-2006)Get full text
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미세변화증후군 환자에서 말기신부전으로 진행한 Chinese Herb Nephropathy
Published in Kidney research and clinical practice (30-01-2006)Get full text
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A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control
Published in IEEE journal of solid-state circuits (01-05-2022)“…A fifth-generation (5G) frequency range 2 (FR2) transmitter front end with a fully integrated power detector for enabling closed-loop power control is…”
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A Case of Mitochondrial Myopathy With Cardiac Involvement
Published in Korean circulation journal (2008)“…Mitochondrial myopathy is a disease caused by structural, biochemical or genetic disturbance of the mitochondria and this affects many organs, and it may also…”
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A 28-nm 75-fsrms Analog Fractional- N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
Published in IEEE journal of solid-state circuits (01-05-2019)“…An analog fractional-<inline-formula> <tex-math notation="LaTeX">N </tex-math></inline-formula> sampling phase-locked loop (PLL) is presented. It achieves…”
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A 28-nm 75-fsrms Analog Fractional-[Formula Omitted] Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
Published in IEEE journal of solid-state circuits (01-01-2019)“…An analog fractional-[Formula Omitted] sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a…”
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Frequency-domain equalization for distributed terrestrial DTV transmission environments
Published in 2006 Digest of Technical Papers International Conference on Consumer Electronics (2006)“…This paper presents a frequency-domain direct-inversion equalization method for DTV receivers to deal with 0 dB ghosts. To secure the existence of a channel…”
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Conference Proceeding -
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A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW
Published in 2022 IEEE International Solid- State Circuits Conference (ISSCC) (20-02-2022)“…The 5G NR frequency band 2 (FR2) standard has evolved to support mm-wave bands spanning from 24 to 40 GHz. Single-band phased-array beam-forming ICs (BFIC)…”
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Conference Proceeding -
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A Flexible Control and Calibration Architecture Using RISC-V MCU for 5G Millimeter-wave Mobile RF Transceivers
Published in 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (01-08-2020)“…We propose an architecture for mobile RF transceivers which integrates RISC-V micro-controller unit (MCU) to control its internal function without requiring…”
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Conference Proceeding