Search Results - "Samudra, G S"

Electrostatics of Ultimately Thin-Body Tunneling FET Using Graphene Nanoribbon by Kai-Tak Lam, Yue Yang, Samudra, G S, Yee-Chia Yeo, Gengchiau Liang

“…The effect of 2-D electrostatic environment on the device performance of ultimately thin-body tunneling field-effect transistors (UTB-TFETs) using graphene…”
Get full text

Mechanism of Stress Memorization Technique (SMT) and Method to Maximize Its Effect by Pandey, S M, Liu, J, Hooi, Z S, Flachowsky, S, Herrmann, T, Tao, W, Benistant, F, See, A, Chu, S, Samudra, G S

“…A simple and unified fundamental theory on the mechanism of stress memorization technique (SMT) is presented for the first time. This theory is based on the…”
Get full text

Two-Dimensional Discontinuous Galerkin Time-Domain Method for Modeling of Arbitrarily Shaped Power-Ground Planes by Hui Min Lee, Siping Gao, En-Xiao Liu, Samudra, G. S., Er-Ping Li

“…This paper presents a two-dimensional discontinuous Galerkin time-domain (2-D DGTD) method for modeling arbitrarily shaped power-ground planes in high-speed…”
Get full text

Low noise RF MOSFETs on flexible plastic substrates by Kao, H.L., Chin, A., Hung, B.F., Lee, C.F., Lai, J.M., McAlister, S.P., Samudra, G.S., Won Jong Yoo, Chi, C.C.

“…We report a low minimum noise figure (NF min ) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-μm RF MOSFETs, after thinning down…”
Get full text

Power integrity modeling and measurement of TSV-based 3D IC system with application to the analysis of seven-chip stack by Lee, Hui Min, Liu, En-Xiao, Samudra, G.S., Li, Er-Ping, Li, Hong Yu, Teo, Keng Hwa

“…This paper presents power integrity modeling and measurement of through-silicon via (TSV)-based 3D IC system. To leverage the accuracy of a full-wave approach…”
Get full text

N-channel FinFETs With 25-nm Gate Length and Schottky-Barrier Source and Drain Featuring Ytterbium Silicide by Lee, R.T.P., Lim, A.E.-J., Kian-Ming Tan, Tsung-Yang Liow, Guo-Qiang Lo, Samudra, G.S., Dong Zhi Chi, Yee-Chia Yeo

“…We have fabricated n-channel 25-nm gate length FinFETs with Schottky-barrier source and drain featuring a self-aligned ytterbium silicide (YbSi 1.8 ). A…”
Get full text

A set of analytic formulas for capacitance of VLSI interconnects of trapezium shape by Samudra, G.S., Hsio Lin Lee

“…In VLSI timing analysis, a quick and accurate extraction of interconnect line to line and line to ground capacitance is very important. This paper presents a…”
Get full text

Global optimization for digital MOS circuits performance by Chen, H.M., Samudra, G.S., Chan, D.S.H., Ibrahim, Y.

“…Apart from maximization of parametric yield, minimization of the spread in performance functions due to process variation is of extreme importance in very…”
Get full text

Trends in DRAM dielectrics by Tang, K.S., Lau, W.S., Samudra, G.S.

“…We trace the development of the ON/ONO dielectric film and examine the potential of new dielectrics with high dielectric constants such as Ta/sub 2/O/sub 5/…”
Get full text

Tunable oxide-bypassed trench gate MOSFET: breaking the ideal superjunction MOSFET performance line at equal column width by Xin Yang, Liang, Y.C., Samudra, G.S., Yong Liu

“…The superjunction (SJ) MOSFET power device is recognized for its higher blocking capability and lower on-state resistance that break the conventional unipolar…”
Get full text

A simple technology for superjunction device fabrication: polyflanked VDMOSFET by Kian Paau Gan, Xin Yang, Liang, Y.C., Samudra, G.S., Liu Yong

“…The charge compensation based novel superjunction (SJ) MOSFET outperforms its conventional counterparts. However, the production of SJ devices is limited by a…”
Get full text

Direct extraction of substrate network parameters for RF MOSFET modeling using a simple test structure by Mahalingam, U., Rustagi, S.C., Samudra, G.S.

“…This letter presents a novel test structure to accurately extract the substrate network parameters for RF MOSFET modeling from two-port measurements. The test…”
Get full text

Accurate current sensor for lateral IGBT smart power integration by Liang, Y.C., Samudra, G.S., Lim, A.J.D., Pick Hong Ong

“…This paper describes research work on the design and fabrication of a current sensor suitable for smart power integration in lateral insulated-gate bipolar…”
Get full text

Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices by Liang, Y.C., Gan, K.P., Samudra, G.S.

“…The superjunction concept has been proposed to overcome the ideal silicon MOSFET limit, but its fabrication was handicapped by the precise charge balance…”
Get full text

SDODEL MOSFET for performance enhancement by King Jien Chui, Samudra, G.S., Yee-Chia Yeo, Kheng-Chok Tee, Leong, K.-W., Kian Meng Tee, Benistant, F., Lap Chan

“…A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated…”
Get full text

Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current by Peng-Fei Guo, Li-Tao Yang, Yue Yang, Lu Fan, Gen-Quan Han, Samudra, G.S., Yee-Chia Yeo

“…We report the first study of the effect of strain on tunneling field-effect transistor (TFET) characteristics. Double-gate silicon TFETs were employed. It was…”
Get full text

Power integrity modeling, measurement and analysis of seven-chip stack for TSV-based 3D IC integration by Hui Min Lee, En-Xiao Liu, Samudra, G. S., Er-Ping Li

“…This paper presents power integrity modeling, measurement and analysis of a seven-chip stack for through-silicon via (TSV)-based 3D IC integration. A hybrid…”
Get full text

Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs by Sai-Kong Chin, Dawei Seah, Kai-Tak Lam, Samudra, G S, Gengchiau Liang

“…We present a detailed simulation study on the current-voltage characteristics of ballistic graphene nanoribbon (GNR) tunneling FETs of different widths with…”
Get full text

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance by Hui Min Lee, Er-Ping Li, En-Xiao Liu, Samudra, G. S.

“…Impact caused by Through-Silicon Via (TSV) induced thermo-mechanical stress on device performance has been a concern for three-dimensional (3D) integrated…”
Get full text

Strain-induced very low noise RF MOSFETs on flexible plastic substrate by Kao, H.L., Chin, A., Hung, B.F., Lai, J.M., Lee, C.F., Li, M.-F., Samudra, G.S., Zhu, C., Xia, Z.L., Liu, X.Y., Kang, J.F.

“…Using microstrip line design to screen substrate resistance generated RF noise, very low 1.1 dB min. noise figure (NF/sub min/) and high 12 dB associate gain…”
Get full text