Search Results - "Sameni, P."

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  1. 1

    Modeling of MOS varactors and characterizing the tuning curve of a 5-6 GHz LC VCO by Sameni, P., Siu, C., Iniewski, K., Hamour, M., Mirabbasi, S., Djahanshahi, H., Chana, J.

    “…A novel accumulation-mode MOS varactor model used for characterizing the tuning curve of LC-tank voltage-controlled oscillators (VCOs) is presented. The VCO…”
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    Conference Proceeding
  2. 2

    A 1/8-rate clock and data recovery architecture for high-speed communication systems by Sameni, P., Mirabbasi, S.

    “…A new clock and data recovery (CDR) architecture for high-speed communication applications is introduced. The proposed CDR architecture is described in the…”
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    Conference Proceeding
  3. 3
  4. 4

    A fully differential high-speed double-edge triggered flip-flop (DETFF) by Sameni, P., Mirabbasi, S.

    “…A high-speed double-edge-triggered flip-flop designed in 0.18 /spl mu/m CMOS technology is presented. Flip-flops, to a large extent, determine the speed of…”
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    Conference Proceeding
  5. 5

    Characterization and modeling of accumulation-mode MOS varactors by Sameni, P., Siu, C., Iniewski, K., Mirabbasi, S., Djahanshahi, H., Hamour, M., Chana, J.

    “…The characterization and modeling of an accumulation-mode MOS varactor implemented in a standard 0.13 mum CMOS process is discussed. An experimental model…”
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    Conference Proceeding