Search Results - "Sam, D. S. Shylu"

Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process by Sam, D S Shylu, Sam Paul, P, Jingle, Diana Jeba, Paul, P Mano, Samuel, Judith, Reshma, J, Sudeepa, P Sarah, Evangeline, G

“…This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used…”
Get full text

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique by Sam, D.S. Shylu, Paul, P. Sam

“…Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various…”
Get full text

Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers by Shylu Sam, D. S., Sam Paul, P., Enoch Mani Deepak, B., Shirley Eva Paul, B., Jayanth, B., Pavitra Kumar, K.

“…There is a rapid growth in semiconductor technology as the need for digital application systems has  increased. Arithmetic operations such as addition and…”
Get full text

Differential Voltage Controlled Ring VCO with No Feedback Loop Technique for Radio Frequency Applications by D., Persiya Gnana Golda, Sam, D.S. Shylu, Paul, P.Sam, Jayanthi, D., Nivetha, G.

“…The essential parts of such as phase-locked loops, signal generators, and signal processors are oscillators. VCOs need to be carefully designed because they…”
Get full text

Design of High-Performance Carry Select Adder using Multiplexer based Logic in 90nm Technology by Wesly, Kanugula John, Rajesh, Sompalli, Rajeswaran, Minnadivel Raj, Naidu, Muttaluru Aswartha, Grace, Ruby, Sam, D S. Shylu

“…To design a high-speed SqRt CSLA(Square Root Carry Select Look Ahead Adder) by using Multiplexer logic in order to reduce the number of gates. Performance…”
Get full text

Verification of UART using AHB VIP with Maximum Coverage by D, Persiya Gnana Golda, Percy Deborah, S., J., Suji Sharon, Shylu Sam, D.S., Sam Paul, P., Jayanthi, D., S., Ansia Liji K., Nivetha, G.

“…Universal Asynchronous Receiver Transmitter is a serial communication protocol that helps in communicating data between devices. The verification of UART is…”
Get full text

Design and Analysis of Frequency Synthesizer for Implantable Cardioverter Defibrillator (ICD) in 90 NM Technology by Babafakruddin, Shaik, Manoj, G, Samson Immanuel, J, Shylu Sam, D. S., Durai Balaji, R, Shriashwinraja E G, V

“…This article briefs on a low power 450 MHz a PLL-based frequency synthesizer for implantable medical devices (IMD). The technological devices inserted into…”
Get full text

Design of Low Power Pass Transistor Logic Based Adders for Multiplier in 90nm CMOS Process by R, Durai Balaji, Shylu Sam, D.S., G, Manoj, Jayanthi, D., J, Samson Immanuel, Babafakruddin, Shaik, V, Shriashwinraja E G

“…The goal of this work is to design a half adder circuit for a multiplier with the considerations of low power dissipation and area reduction under the supply…”
Get full text

A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique by Sam, D.S.Shylu, Moni, D. Jackuline, Paul, P. Sam, Nirmal, D.

“…This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon-based CMOS process. Simultaneous capacitor sharing and…”
Get full text

Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process by Sam, D. S. Shylu, Sam Paul, P., Jingle, Diana Jeba, Paul, P. Mano, Samuel, Judith, Reshma, J., Sudeepa, P. Sarah, Evangeline, G.

Get full text

Design and Analysis of Two Stage Op-Amp in 180nm CMOS Process by V., Smrithi, Sam, D.S.Shylu, Manoj, G.

“…Operational amplifiers are an integral part of an electronic system. Typical uses of the operational amplifier are amplifiers, oscillators, filters and also…”
Get full text

A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process by Shylu Sam, D. S., Paul, P. Sam, Jayanthi, D.

“…Based on the 0.18 \mu m 1.8V CMOS process, a novel architecture of folded cascode operational transconductance amplifier (OTA) is designed for a 10-bit…”
Get full text

Design of highly reusable interface for AHB verification module by Mahendra, Vignesh T, Shylu Sam, D.S., Hernisha, A J, Atchaya, A Josephine

“…Bus protocols are critical for the operation of a system as all communications are handled through the bus by following a predetermined structure. An IP is…”
Get full text

Design of Low Power Dynamic Comparator for SAR ADC by Herinsha, A J, Shylu Sam, D.S., Atchaya, A Josephine, Vignesh T, Mahendra

“…This work is based on a low power comparator design for SAR ADCs. The pre-amplifier uses an inverter-based input pair with a floater reservoir capacitor to…”
Get full text

Design of High Speed Time - Interleaved SAR Analog to Digital Converter by Atchaya, A Josephine, Shylu Sam, D.S., Herinsha, A J, Mahendra, Vignesh T

“…The design approaches for high-speed SAR ADCs are discussed in this work. It's an interleaving architecture with a fast coarse successive approximation…”
Get full text