Search Results - "Sallese, J. M."

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  1. 1

    Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime by Jazaeri, F., Barbut, L., Koukab, A., Sallese, J.-M.

    Published in Solid-state electronics (01-04-2013)
    “…► Junctionless is one of the most promising alternative architecture for CMOS. ► Some works have been done via numerical simulations. ► An analytical model of…”
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    Journal Article
  2. 2

    On performance scaling and speed of junctionless transistors by Koukab, A., Jazaeri, F., Sallese, J.-M.

    Published in Solid-state electronics (01-01-2013)
    “…► We propose a prospective study of the junctionless transistors (JLTs) scaling performances. ► Analytical evaluation of the JLT intrinsic delay, after…”
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  3. 3

    Theoretical Studies of Nanowire Ion-Sensitive Field Effect Transistor by Yesayan, A., Petrosyan, S., Papiyan, A., Sallese, J.-M.

    Published in Journal of contemporary physics (01-10-2021)
    “…The operation principle of a semiconductor nanowire (NW) ion-sensitive field-effect transistor (ISFET), denoted for pH sensing, is studied within the framework…”
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  4. 4

    Role of the gate in ballistic nanowire SOI MOSFETs by Mangla, A., Sallese, J.-M., Sampedro, C., Gamiz, F., Enz, C.

    Published in Solid-state electronics (01-10-2015)
    “…In this paper we report the results of Monte-Carlo simulations performed on double-gate ballistic MOSFETs with a geometry such that the gates overlap only a…”
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  5. 5

    Design and modeling of self-aligned nano-imprinted sub-micrometer pentacene-based organic thin-film transistors by Zanella, F., Marjanović, N., Ferrini, R., Gold, H., Haase, A., Fian, A., Stadlober, B., Müller, R., Genoe, J., Hirshy, H., Drost, A., König, M., Lee, K.-D., Ring, J., Prétôt, R., Enz, C.C., Sallese, J.-M.

    Published in Organic electronics (01-11-2013)
    “…[Display omitted] •Organic thin-film transistors (OTFTs) with sub-micrometer channel length.•Self-aligned gate/source–drain contacts.•Field-effect mobility…”
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  6. 6

    Transient current technique for charged traps detection in silicon bonded interfaces by Bronuzzi, J., Bouvet, D., Charrier, C., Fournel, F., García, M. F., Mapelli, A., Moll, M., Rouchouze, E., Sallese, J. M.

    Published in AIP advances (01-02-2019)
    “…Wafer bonding is an established technology for the manufacturing of silicon-on-insulator (SOI) substrates, micro-electromechanical systems (MEMS) and…”
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  7. 7

    A capacitor-less 1T-DRAM cell by Okhonin, S., Nagoga, M., Sallese, J.M., Fazan, P.

    Published in IEEE electron device letters (01-02-2002)
    “…A simple true 1 transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI…”
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  8. 8

    Radiation response of 28 nm CMOS transistors at high proton and neutron fluences for high energy physics applications by Termo, G., Borghello, G., Faccio, F., Michelis, S., Koukab, A., Sallese, J.M.

    “…The 28 nm CMOS technology was selected as a promising candidate to upgrade electronics of particle detectors at CERN. Despite the robustness of this node to…”
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  9. 9

    Explicit Compact Model for Ultranarrow Body FinFETs by Mingchun Tang, Pregaldiny, F., Lallement, C., Sallese, J.-M.

    Published in IEEE transactions on electron devices (01-07-2009)
    “…An explicit charge-based compact model for lightly doped FinFETs is proposed. This design-oriented model is valid and continuous in all operating regimes…”
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  10. 10

    Noise modeling methodologies in the presence of mobility degradation and their equivalence by Roy, A.S., Enz, C.C., Sallese, J.-M.

    Published in IEEE transactions on electron devices (01-02-2006)
    “…For compact modeling of the noise in devices, one of the following three methods is usually applied: 1) An equivalent circuit based approach, 2) the classical…”
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  11. 11

    Noise Modeling in Lateral Nonuniform MOSFET by Roy, A.S., Enz, C.C., Sallese, J.-M.

    Published in IEEE transactions on electron devices (01-08-2007)
    “…In this paper, we present an analytical noise modeling methodology for lateral nonuniform MOSFET. We demonstrate that the noise properties of lateral…”
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  12. 12

    A closed-form charge-based expression for drain current in symmetric and asymmetric double gate MOSFET by Roy, A.S., Sallese, J.M., Enz, C.C.

    Published in Solid-state electronics (01-04-2006)
    “…Although both exact [Taur Y, Liang X, Wang W, Lu H. A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Dev Lett 2004;25(2):399–401] and…”
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    Journal Article Conference Proceeding
  13. 13

    SOI Pixel Based on a Floating Body Partially Depleted MOSFET in a Delta-Sigma Loop by Harik, L., Sallese, J.-M., Kayal, M.

    Published in IEEE sensors journal (01-08-2009)
    “…Standard techniques used for measuring the photocurrent of an SOI phototransistor have failed due to two main reasons: the first being the low signal-to-noise…”
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  14. 14

    New architecture for the analog front-end of Medipix4 by Sriskaran, V., Alozy, J., Ballabriga, R., Campbell, M., Egidos, N., Fernandez-Tenllado, J.M., Heijne, E., Kremastiotis, I., Koukab, A., Llopart, X., Sallese, J.M., Tlustos, L.

    “…The Medipix4 chip is the latest member of the family of Medipix pixel detector readout chips aimed at high rate spectroscopic X-ray imaging. Unlike its…”
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  15. 15

    The ferroelectric MOSFET: a self-consistent quasi-static model and its implications by Sallese, J.-M., Meyer, V.

    Published in IEEE transactions on electron devices (01-12-2004)
    “…We report a new approach to modeling the metal-ferroelectric-insulator field-effect transistor (MFIS-FET) that leads to a physical understanding of the device…”
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  16. 16

    Compact modeling of gate sidewall capacitance of DG-MOSFET by Roy, A.S., Enz, C.C., Sallese, J.M.

    Published in IEEE transactions on electron devices (01-10-2006)
    “…Recent studies show that the gate sidewall capacitance of an underlap double gate device plays an important role in the design and optimization of the device…”
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  17. 17

    Compact Modeling of Anomalous High-Frequency Behavior of MOSFET's Small-Signal NQS Parameters in Presence of Velocity Saturation by Roy, A.S., Enz, C.C., Sallese, J.-M.

    Published in IEEE transactions on electron devices (01-09-2006)
    “…This paper presents a physical charge-based compact small-signal nonquasi-static (NQS) model for MOST, including velocity saturation and valid in all regions…”
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  18. 18

    A compact non-quasi-static extension of a charge-based MOS model by Porret, A.-S., Sallese, J.-M., Enz, C.C.

    Published in IEEE transactions on electron devices (01-08-2001)
    “…This paper presents a new and simple compact model for the intrinsic metal oxide semiconductor (MOS) transistor, which accurately takes into account the non…”
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  19. 19

    Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model by Lallement, C., Sallese, J.-M., Bucher, M., Grabinski, W., Fazan, P.C.

    Published in IEEE transactions on electron devices (01-02-2003)
    “…This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate…”
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    Journal Article
  20. 20

    Charge, current, and noise partitioning in MOSFET in the presence of mobility degradation by Roy, A.S., Enz, C.C., Sallese, J.M.

    Published in IEEE electron device letters (01-08-2006)
    “…The Ward-Dutton (WD) partitioning scheme is used extensively to develop transient and high-frequency advanced compact models in MOSFET analysis. However, it…”
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