Search Results - "Saif, Sherif"

K-medoid clustering containerized allocation algorithm for cloud computing environment by AbdElSamea, Amany, Saif, Sherif M.

“…Load balancing is critical for container-based cloud computing environments for several reasons. A lack of appropriate load balancing techniques could result…”
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The Impact of Visualization Dashboards on Quality of Care and Clinician Satisfaction: Integrative Literature Review by Khairat, Saif Sherif, Dukkipati, Aniesha, Lauria, Heather Alico, Bice, Thomas, Travers, Debbie, Carson, Shannon S

“…Intensive Care Units (ICUs) in the United States admit more than 5.7 million people each year. The ICU level of care helps people with life-threatening illness…”
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Pareto front analog layout placement using Satisfiability Modulo Theories by Saif, Sherif M., Dessouky, Mohamed, El-Kharashi, M. Watheq, Abbas, Hazem, Nassar, Salwa

“…This paper presents an analog layout placement tool with emphasis on Pareto front generation. In order to handle the exploding number of analog physical…”
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Fog Node Optimum Placement and Configuration Technique for VANETs by Shahin, Rehab, El-Moursy, Ali A., Saif, Sherif M., Abbas, Hazem M., Nassar, Salwa M.

“…Intelligent Transportation Systems (ITS) are nowadays considered very important applications of smart cities. One of the most important technologies that are…”
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Fog-ROCL: A Fog based RSU Optimum Configuration and Localization in VANETs by Shahin, Rehab, Saif, Sherif M., El-Moursy, Ali A., Abbas, Hazem M., Nassar, Salwa M.

“…Intelligent Transportation Systems (ITS) are one of the pillars of smart cities that enable smart traffic and smart mobility. Vehicular Ad-hoc Networks…”
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Hardware Acceleration of Lane Detection Algorithm: A GPU Versus FPGA Comparison by Alshemi, Mohamed, Saif, Sherif, Taher, Mohamed

“…A Complete Computer vision system can be divided into two main categories: detection and classification. The Lane detection algorithm is a part of the computer…”
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A UVM-based Verification Approach for MIPI DSI Low-Level Protocol layer by Ali, Ahmed Mohamed, Shalaby, Ahmed, Saif, Sherif, Taher, Mohamed

“…Display Serial Interface (DSI) is a high-speed serial interface standard. It supports display and touch screens in mobile devices such as smartphones, laptops,…”
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Analog layout placement retargeting using Satisfiability Modulo Theories by Mohamed, Aya, Dessouky, Mohamed, Saif, Sherif M.

“…This paper presents an efficient methodology for automatic analog layout process retargeting, which fits in the current design flow. It relies on two concepts:…”
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An FPGA implementation of a neural optimization of block truncation coding for image/video compression by Saif, Sherif, Abbas, Hazem M., Nassar, Salwa M., Wahdan, Abdelmonem A.

“…This paper presents a Field Programmable Gate Array (FPGA) implementation for image/video compression using an improved block truncation coding (BTC) image…”
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Multi-device layout templates for nanometer analog design by Elshawy, Mohannad, Dessouky, Mohamed, Saif, Sherif, Mansour, Sherif, Petrus, Ed

“…With the advance of nanoscale fabrication processes, well-known common-centroid analog layout techniques are no longer sufficient to guarantee the required…”
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Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories by Saif, Sherif M., Dessouky, Mohamed, Abbas, Hazem, El-Kharashi, M. Watheq, Nassar, Salwa

“…This paper exploits one of the formal methods to generate layouts for an analog circuit, where these layouts satisfy some given analog constraints. The analog…”
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Exploiting satisfiability modulo theories for analog layout automation by Saif, Sherif M., Dessouky, Mohamed, Nassar, Salwa, Abbas, Hazem, El-Kharashi, M. Watheq, Abdulaziz, Mohammad

“…This paper explores the use of Satisfiability Modulo Theories to handle mirror symmetry and common-centroid analog layout placement constraints. The proposed…”
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An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization by Saif, S.M., Abbas, H.M., Nassar, S.M.

“…This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram…”
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An FPGA Implementation of a Hopfield Optimized Block Truncation Coding by Saif, S., Abbas, H.M., Nassar, S.M., Wahdan, A.A.

“…This paper presents an implementation for image compression using variable block truncation coding (BTC) on a field programmable gate array (FPGA). The…”
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FPGA implementation of block truncation coding algorithm for gray scale and color images by Saif, S.M., Nassar, S., Abbas, H.M., Soliman, A.T.

“…This paper presents a field programmable gate array (FPGA) implementation for video compression using block truncation coding (BTC) image compression technique…”
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