Search Results - "Sahu, Chitrakant"

Charge-Plasma Based Process Variation Immune Junctionless Transistor by Sahu, Chitrakant, Singh, Jawar

“…In this letter, we report for the first time a distinctive approach of implementing a junctionless transistor (JLT) without doping (doping-less) the ultrathin…”
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PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET by Lahgere, Avinash, Sahu, Chitrakant, Singh, Jawar

“…This paper presents a new design of dopingless dynamically configurable double-gate tunnel FET (TFET) for process-voltage-temperature (PVT)-aware applications…”
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Analysis of AlGaN/GaN HEMT and Its Operational Improvement Using a Grated Gate Field Plate by Bhat, Aasif Mohammad, Shafi, Nawaz, Sahu, Chitrakant, Periasamy, C.

“…This paper investigates the DC and RF performance of a gate field plate (GFP) and proposed grated gate field plate (GGFP) AlGaN/GaN high electron mobility…”
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Detection of false data injection in smart grid using PCA based unsupervised learning by Sharma, Richa, Joshi, Amit M., Sahu, Chitrakant, Nanda, Satyasai Jagannath

“…Advanced metering infrastructure (AMI) is one of the core aspects of the smart grid, and offers numerous possible benefits, such as load control and demand…”
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Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications by Sirohi, Ankit, Sahu, Chitrakant, Singh, Jawar

“…In this paper, we investigated the performance of a dopingless (DL) double gate field-effect transistor (DL-DGFET) for ultra-low power (ULP) analog/RF…”
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Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications by Sahu, Chitrakant, Singh, Jawar

“…In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film…”
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Influence of dielectric material near tunnel junction on analog/RF and linearity figure of merits in hetero dielectric (HG) TFET: A detailed study by Saha, Rajesh, Sahu, Chitrakant

“…In this work, the effect of dielectric material near the source region on analog/RF and linearity figure of merits in hetero gate TFET (HG‐TFET) are…”
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Impact of interface trap charges on analog/RF and linearity performances of PGP negative capacitance FET by Chaudhary, Shalini, Dewan, Basudha, Singh, Devenderpal, Sahu, Chitrakant, Yadav, Menka

“…Here, we examine the impact of various trap charges on the baseline and NC PGPFET (negative capacitance partial ground plane FET) by applying localized charges…”
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Fabrication and pH Sensitivity Analysis of In-Situ Doped Polycrystalline Silicon Thin-Film Junctionless BioFET by Shafi, Nawaz, Sahu, Chitrakant, Periasamy, C.

“…In this letter, we demonstrate a low cost, CMOS compatible fabrication approach for the development of a back gate controlled, in situ -doped polysilicon…”
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Design and Performance Projection of Virtually Doped Dual Gate Junctionless IMOS by Srikanya, Dasari, Shafi, Nawaz, Sahu, Chitrakant

“…This research investigates the virtually doped dual gate junctionless impact ionization MOS (DG-JL-IMOS). Virtually doped source and drain regions are realized…”
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Fabrication and pH Sensing Characteristics Measurement of Back Gate ZnO Thin Film Planar FET by Porwal, Ankita, Shafi, Nawaz, Sahu, Chitrakant

“…Here in we demonstrate the design of a low-cost zinc oxide (ZnO) thin-film planar transistor-based pH sensor controlled by the bottom gate fabricated by a…”
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Analytical Modeling of Surface Potential and Drain Current for Virtually Doped Symmetrical Dielectric Modulated BioFET by Shafi, Nawaz, Sahu, Chitrakant, Periasamy, C.

“…Herein we investigate the design considerations for virtually doped, symmetric cavity dielectric modulated BioFET through developed surface potential and drain…”
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Electrical Characterization and Study of Current Drift Phenomena and Hysteresis Mechanism in Junctionless Ion-Sensitive Field-Effect Transistor by Parmar, Jaydeep Singh, Shafi, Nawaz, Sahu, Chitrakant

“…A comprehensive study of the drain current drift mechanism and hysteresis phenomena in fabricated p-channel junctionless ion-sensitive field-effect transistor…”
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A comprehensive simulation study on dual segment AlGaN/GaN HEMT for mercury ion detection: Addressing steric hindrance and interfering ions by Poonia, Ritu, Periasamy, C., Bhat, Aasif Mohammad, Bhargava, Lava, Sahu, Chitrakant

“…This study compares the effectiveness of a single sensing segment (Sensor A) and a dual sensing segment (Sensor B), AlGaN/GaN HEMTs, for mercury ion detection…”
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AlGaN/GaN HEMT pH Sensor Simulation Model and Its Maximum Transconductance Considerations for Improved Sensitivity by Bhat, Aasif Mohammad, Shafi, Nawaz, Sahu, Chitrakant, Periasamy, C.

“…In this work, AlGaN/GaN high electron mobility transistor (HEMT) pH sensing simulation model is presented along with the sensitivity analysis to different pH…”
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Performance Assessment of AlGaN/GaN HEMT for Human Serum Albumin Detection Using Charge Deduction Methodology by Poonia, Ritu, Periasamy, C., Bhat, Aasif Mohammad, Bhargava, Lava, Sahu, Chitrakant

“…This article investigates the applicability of an open-gated high-electron-mobility transistor (HEMT) as a biosensing platform for human serum albumin (HSA)…”
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Hydrogen-ion Sensing Characteristics of Cavity Based Triple-Gate Junctionless Biofet for Enhanced Sensitivity by Parmar, Jaydeep Singh, Shafi, Nawaz, Sahu, Chitrakant

“…In this paper, a triple gate (TG) cavity based, polysilicon junctionless (JL) ion-sensitive field-effect transistor (ISFET) architecture has been proposed for…”
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Effect of Negative Capacitance in Partially Ground Plane based SELBOX FET on Capacitance Matching and SCEs: Design, Simulation and Performance Investigation by Chaudhary, Shalini, Dewan, Basudha, Sahu, Chitrakant, Yadav, Menka

“…Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET)…”
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Temperature sensitivity analysis of dopingless charge-plasma transistor by Shrivastava, Vishwas, Kumar, Anup, Sahu, Chitrakant, Singh, Jawar

“…The junctionless field-effect transistors (JLFETs) have shown potential to scale down in sub-10nm regime due to simplified fabrication process and less…”
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Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor by Sahu, Chitrakant, Singh, Jawar

“…In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results…”
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