Search Results - "Sachid, Angada B"

High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors by Tosun, Mahmut, Chuang, Steven, Fang, Hui, Sachid, Angada B, Hettick, Mark, Lin, Yongjing, Zeng, Yuping, Javey, Ali

“…In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is…”
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Field-Effect Transistors Built from All Two-Dimensional Material Components by Roy, Tania, Tosun, Mahmut, Kang, Jeong Seuk, Sachid, Angada B, Desai, Sujay B, Hettick, Mark, Hu, Chenming C, Javey, Ali

“…We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor,…”
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Monolithic 3D CMOS Using Layered Semiconductors by Sachid, Angada B., Tosun, Mahmut, Desai, Sujay B., Hsu, Ching-Yi, Lien, Der-Hsien, Madhvapathy, Surabhi R., Chen, Yu-Ze, Hettick, Mark, Kang, Jeong Seuk, Zeng, Yuping, He, Jr-Hau, Chang, Edward Yi, Chueh, Yu-Lun, Javey, Ali, Hu, Chenming

“…Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low‐temperature processing are reported. A variety of digital and analog…”
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Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization by Sachid, A.B., Manoj, C.R., Sharma, D.K., Rao, V.R.

“…The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate…”
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MoS₂ transistors with 1-nanometer gate lengths by Desai, Sujay B., Madhvapathy, Surabhi R., Sachid, Angada B., Llinas, Juan Pablo, Wang, Qingxiao, Ann, Geun Ho, Pitner, Gregory, Kim, Moon J., Bokor, Jeffrey, Hu, Chenming, Wong, H.-S. Philip, Javey, Ali

“…Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si,…”
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Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors by Kwon, Daewoong, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Zhou, Hong, Sachid, Angada B., Reis, Roberto Dos, Hu, Chenming, Salahuddin, Sayeef

“…Negative capacitance (NC) FETs with channel lengths from 30 nm to <inline-formula> <tex-math notation="LaTeX">50~\mu \text{m} </tex-math></inline-formula>,…”
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Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits by Pal, Ashish, Sachid, Angada B, Gossner, Harald, Rao, V Ramgopal

“…Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase…”
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High-gain monolithic 3D CMOS inverter using layered semiconductors by Sachid, Angada B., Desai, Sujay B., Javey, Ali, Hu, Chenming

“…We experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide…”
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Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights by Sachid, A. B., Chenming Hu

“…We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of…”
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Variation Caused by Spatial Distribution of Dielectric and Ferroelectric Grains in a Negative Capacitance Field-Effect Transistor by Kao, Ming-Yen, Sachid, Angada B., Lin, Yen-Kai, Liao, Yu-Hung, Agarwal, Harshit, Kushwaha, Pragya, Duarte, Juan Pablo, Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming

“…We propose a new scheme to consider the dielectric (DE) phases inside polycrystalline ferroelectric (FE) materials. The scheme is used to extract material…”
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Modeling of Back-Gate Effects on Gate-Induced Drain Leakage and Gate Currents in UTB SOI MOSFETs by Yen-Kai Lin, Kushwaha, Pragya, Agarwal, Harshit, Huan-Lin Chang, Duarte, Juan Pablo, Sachid, Angada B., Khandelwal, Sourabh, Salahuddin, Sayeef, Chenming Hu

“…The back-gate bias-dependent gate-induced drain leakage (GIDL) and gate current models of ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are proposed…”
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Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect by Zhou, Hong, Kwon, Daewoong, Sachid, Angada B., Liao, Yuhung, Chatterjee, Korok, Tan, Ava J., Yadav, Ajay K., Hu, Chenming, Salahuddin, Sayeef

“…We report on negative capacitance (NC) FinFETs with ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI)…”
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A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET by Shrivastava, M., Baghini, M.S., Sachid, A.B., Sharma, D.K., Rao, V.R.

“…In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate…”
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Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs by Manoj, C.R., Sachid, A.B., Feng Yuan, Chang-Yun Chang, Rao, V.R.

“…In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this…”
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Drain current model for nanoscale double-gate MOSFETs by Hariharan, Venkatnarayan, Thakker, Rajesh, Singh, Karmvir, Sachid, Angada B., Patil, M.B., Vasi, Juzer, Rao, V. Ramgopal

“…A closed form inversion charge-based drain current model for a short channel symmetrically driven, lightly doped symmetric double-gate MOSFET (SDGFET) is…”
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FinFET With High- \kappa Spacers for Improved Drive Current by Sachid, Angada B., Min-Cheng Chen, Chenming Hu

“…We demonstrate p-channel gate-source/drain underlapped silicon FinFET with HfO 2 high-κ spacer and compare it with its counterpart having SiO 2 low-κ spacer…”
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Bulk FinFET With Low- \kappa Spacers for Continued Scaling by Sachid, Angada B., Min-Cheng Chen, Chenming Hu

“…We fabricate n-channel silicon bulk FinFET with silicon nitride (Si 3 N 4 ) high-κ, silicon nitride/silicon dioxide dual-κ, and silicon dioxide (SiO 2 ) low-κ…”
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Engineering Negative Differential Resistance in NCFETs for Analog Applications by Agarwal, Harshit, Kushwaha, Pragya, Duarte, Juan Pablo, Lin, Yen-Kai, Sachid, Angada B., Kao, Ming-Yen, Chang, Huan-Lin, Salahuddin, Sayeef, Hu, Chenming

“…In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing <inline-formula> <tex-math notation="LaTeX">{V}_{\mathrm…”
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Nanowire FET With Corner Spacer for High-Performance, Energy-Efficient Applications by Sachid, Angada B., Hsiang-Yun Lin, Chenming Hu

“…Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This…”
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UTBSOI MOSFET with corner spacers for energy-efficient applications by Sachid, Angada B., Hu, Chenming

“…Parasitic capacitance is a critical challenge in improving the device and circuit performance in nanoscale devices like the UTBSOI MOSFET and FinFET. Scaling…”
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