Search Results - "SMEDES, Theo"

Pitfalls for transient response analysis with VF-TLP by Smedes, Theo, Coenen, Mart, Sluiter, Sander, Cappon, Paul

“…Analyzing transient ESD device behavior with TLP equipment requires more attention for implementation and measurement details than the classical quasi-static…”
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An integral injector-victim current transfer model for latchup design rule optimization by Quax, Guido, Smedes, Theo

“…This work introduces a derivative-based model to describe the transfer between injector and victim during negative DC current stress. Geometric variation of…”
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Over-stress and under-stress effects in CDM testing by O'Sullivan, Greg, Smedes, Theo, Derikx, Richard, Garcia, Artemio, Knoppers, Bob

“…This paper describes two mechanisms that can lead to over-stress and/or under-stress when testing ICs for CDM robustness. We show that CDM testing of…”
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High-Voltage ESD Protection Device With Fast Transient Reaction and High Holding Voltage by Lai, Da-Wei, de Raad, Gijs, Sque, Stephen, Peters, Wim, Smedes, Theo

“…A stacked p-n-p(s) and grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) solution, with higher holding voltage (<inline-formula> <tex-math…”
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Gate-Lifted nMOS ESD Protection Device Triggered by a p-n-p in Series With a Diode by Lai, Da-Wei, Sque, Stephen, Peters, Wim, Smedes, Theo

“…We demonstrate a gate-lifted nMOS electrostatic discharge (ESD) protection device triggered by a p-n-p in series with a diode in a 0.18-<inline-formula>…”
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Latchup holding voltages and trigger currents in an SOI technology by Quax, Guido, Smedes, Theo

“…This paper investigates holding voltages and trigger currents in a Silicon-on-Insulator technology. These parameters can be used in automated layout checks…”
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Bidirectional ESD Protection Device Using PNP With pMOS-Controlled Nwell Bias by Lai, Da-Wei, de Raad, Gijs, Tseng, Wei-Jhih, Smedes, Theo, Huitsing, Albert Jan

“…We demonstrate a PNP-based bidirectional ESD protection device with base bias controlled by two pMOS transistors, realized in a 0.18-<inline-formula> <tex-math…”
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CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study by Abessolo-Bidzo, D., Smedes, T., Huitsing, A. J.

“…The electrostatic discharge (ESD) sensitivity of ICs with respect to the charged-device model (CDM) is strongly dependent on the IC package, the substrate…”
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A Statistical Explanation of CDM Qualification Variability by Smedes, Theo, Scheucher, Wolfgang, Verwoerd, Sheela, Verwijst, Joop

“…CDM testing is known to sometimes have qualification reproducibility problems. This paper discusses possible sources of variability and two statistical…”
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On-chip system level protection of FM antenna pin with improved linearity by Notermans, Guido, Maksimovic, Dejan, Vermont, Gerd, Maasakkers, Michiel van, Pusa, Fredrik, Smedes, Theo

“…An on-chip protection against IEC 61000-4-2 discharges is presented. The protection level is tested by means of HMM stress. The failure signature is identified…”
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An ESD test reduction method for complex devices by Maksimovic, Dejan, Blanc, Fabrice, Notermans, Guido, Smedes, Theo, Keller, Thomas

“…We define rules to reduce the ESD test complexity for chips with large pin count. These rules exploit the structural similarity in the pad-ring and have a long…”
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ESD protection for thin gate oxides in 65nm by Notermans, Guido, Smedes, Theo, Mrčarica, Željko, Jong, Peter de, Stephan, Ralph, Zwol, Hans van, Maksimovic, Dejan

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General chairman's welcome

“…Presents the introductory welcome message from the conference proceedings…”
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ESD protection for thin gate oxides in 65 nm by Notermans, Guido, Smedes, Theo, Mrčarica, Željko, Jong, Peter de, Stephan, Ralph, Zwol, Hans van, Maksimovic, Dejan

“…Unexpected functional failures were found in the core of an IC, processed in a 65 nm technology with 1.8 nm gate oxide, after Machine Model (MM) testing,…”
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The HBM Tester Parasitics Problem by Smedes, Theo, Grad, Marcin, Verwoerd, Sheela, Gao, Jian, O'Sullivan, Greg, Davis, James

“…The HBM standard acknowledges that tester behavior may suffer from parasitics, but limited data has been presented. This paper compares several matrix based…”
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Pitfalls for Transient Analysis with VF-TLP by Smedes, Theo, Coenen, Mart, Sluiter, Sander, Cappon, Paul

“…Analyzing transient ESD device behavior with TLP equipment requires more attention for implementation and measurement details than the classical quasi-static…”
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ESD robust high-voltage active clamps by Notermans, Guido, Quittard, Olivier, Heringa, Anco, Mrčarica, Željko, Blanc, Fabrice, Zwol, Hans van, Smedes, Theo, Keller, Thomas, Jong, Peter de

“…Using circuit simulation extended by a proper failure criterion, the HBM and TLP robustness of high-voltage clamps can be accurately predicted without the need…”
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HMM Failure Level Variations Revisited by Dekker, Marcel, Smedes, Theo, Notermans, Guido, Ashton, Robert

“…HMM has been proposed as a standard method to evaluate stand-alone devices with a system level pulse. Mixed results have been published earlier. This paper…”
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Wear out effects in ESD characterization and testing by Smedes, Theo, Abessolo-Bidzo, Dolphin

“…Wear out effects resulting from multiple stresses may have significant impact on ESD characterization and testing. This is shown in examples of (vf-)TLP, HMM…”
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Window effects in HBM and TLP testing by Smedes, Theo, Scheucher, Wolfgang, Abessolo-Bidzo, Dolphin

“…We present a study of products showing systematic window effects during HBM and TLP testing. It is shown that the window effects are mainly the consequence of…”
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