Search Results - "SAKIYAMA, Shiro"
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1
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback
Published in IEEE journal of solid-state circuits (01-06-2010)“…An on-chip CMOS relaxation oscillator with voltage averaging feedback using a reference proportional to supply voltage is presented. A voltage-averaging…”
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Journal Article -
2
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques
Published in IEEE journal of solid-state circuits (01-06-2015)“…This paper presents a SAR ADC with 71 dB SNDR and 85 dB SFDR at 50 MS/s while keeping low power consumption of 4.2 mW. To achieve high resolution without large…”
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Journal Article -
3
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise
Published in 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers (01-02-2013)“…SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent…”
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Conference Proceeding
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4
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System
Published in IEEE journal of solid-state circuits (01-04-2008)“…A practical method for coupled oscillator design is elaborated. The topology analysis of a coupled oscillator, the ways of simulating its sensitivity,…”
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Journal Article Conference Proceeding -
5
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage
Published in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01-02-2009)“…On-chip reference oscillators are required for low-cost single-chip applications including biomedical sensors, microcomputers, high-speed interfaces such as…”
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Conference Proceeding -
6
Mixed body bias techniques with fixed Vt and Ids generation circuits
Published in IEEE journal of solid-state circuits (01-01-2005)Get full text
Journal Article -
7
Mixed body bias techniques with fixed Vt and Idsgeneration circuits
Published in IEEE journal of solid-state circuits (2005)Get full text
Conference Proceeding -
8
An over 20,000 quality factor on-chip relaxation oscillator using Power Averaging Feedback with a Chopped Amplifier
Published in 2010 Symposium on VLSI Circuits (01-06-2010)“…This paper describes the first achievement of over 20,000 quality factors among on-chip relaxation oscillators. The proposed Power Averaging Feedback with a…”
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Conference Proceeding -
9
Mixed body-bias techniques with fixed Vt and Ids generation circuits
Published in 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005 (2005)“…In sub 1 V CMOS VLSIs, the authors proposed a new body bias generation circuits in which Ids and Vt of pMOS/nMOS become always fixed. The mixed body bias…”
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Conference Proceeding -
10
Quantizer neuron model and neuroprocessor-named quantizer neuron chip
Published in IEEE journal on selected areas in communications (01-12-1994)“…A quantizer neuron model and a hardware implementation of the model is described. A quantizer neuron model and a multifunctional layered network (MFLN) with…”
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Journal Article -
11
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization
Published in Proceedings of the 2009 Asia and South Pacific Design Automation Conference (19-01-2009)“…In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the…”
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Conference Proceeding -
12
Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application
Published in 2007 IEEE Symposium on VLSI Circuits (01-06-2007)“…Low power design is essential for mobile application. For a PLL with multiphase outputs, level shifter (LS), which converts oscillator-output-level to that of…”
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Conference Proceeding -
13
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization
Published in 2009 Asia and South Pacific Design Automation Conference (01-01-2009)“…In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the…”
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Conference Proceeding -
14
Mixed body-bias techniques with fixed V1 and Idsgeneration circuits
Published 2004Get full text
Conference Proceeding -
15
High efficiency and latch-up free switched capacitor up converter on FD-SOI technology
Published in 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) (2002)“…We have developed a latch-up free Switched Capacitor (SC) type voltage up converter on 0.35 /spl mu/m FD-SOI technology. In this paper, we propose approximate…”
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Conference Proceeding -
16
A Lean Power Management technique: the lowest power consumption for the given operating speed of LSIs
Published in Symposium 1997 on VLSI Circuits (1997)Get full text
Conference Proceeding