Search Results - "Rynders, L."
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Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node
Published in 2019 IEEE International Electron Devices Meeting (IEDM) (01-12-2019)“…The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full…”
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Conference Proceeding -
2
Process Integration of High Aspect Ratio Vias with a Comparison between Co and Ru Metallizations
Published in 2021 IEEE International Interconnect Technology Conference (IITC) (06-07-2021)“…The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison…”
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Conference Proceeding -
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Supervia Process Integration and Reliability Compared to Stacked Vias Using Barrierless Ruthenium
Published in 2020 IEEE International Electron Devices Meeting (IEDM) (12-12-2020)“…The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated…”
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4
A 42.5 Mchip/s direct sequence spread spectrum receiver with digital IF and integrated ARM6 core
Published in Proceedings of CICC 97 - Custom Integrated Circuits Conference (1997)“…This paper reports on a direct sequence spread spectrum (DSSS) ASIC, which integrates all the digital functions of an L-band satellite pager. The ASIC performs…”
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Conference Proceeding