Search Results - "Ruhl, Greg"

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS by Jain, S., Khare, S., Yada, S., Ambili, V., Salihundam, P., Ramani, S., Muthukumar, S., Srinivasan, M., Kumar, A., Gb, S. K., Ramanarayanan, R., Erraguntla, V., Howard, J., Vangal, S., Dighe, S., Ruhl, G., Aseron, P., Wilson, H., Borkar, N., De, V., Borkar, S.

“…Near-threshold computing brings the promise of an order of magnitude improvement in energy efficiency over the current generation of microprocessors [1]…”
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2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology by Somasekhar, D., Yibin Ye, Aseron, P., Shih-Lien Lu, Khellah, M.M., Howard, J., Ruhl, G., Karnik, T., Borkar, S., De, V.K., Keshavarzi, A.

“…We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access…”
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The 48-core SCC Processor: the Programmer's View by Mattson, Timothy G, Van der Wijngaart, Rob F, Riepen, Michael, Lehnig, Thomas, Brett, Paul, Haas, Werner, Kennedy, Patrick, Howard, Jason, Vangal, Sriram, Borkar, Nitin, Ruhl, Greg, Dighe, Saurabh

“…The number of cores integrated onto a single die is expected to climb steadily in the foreseeable future. This move to many-core chips is driven by a need to…”
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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS by Hoskote, Y., Bloechel, B.A., Dermer, G.E., Erraguntla, V., Finan, D., Howard, J., Klowden, D., Narendra, S.G., Ruhl, G., Tschanz, J.W., Sriram Vangal, Veeramachaneni, V., Wilson, H., Jianping Xu, Borkar, N.

“…This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This…”
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2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process by Somasekhar, Dinesh, Ye, Yibin, Aseron, Paolo, Lu, Shih-Lien, Khellah, Muhammad, Howard, Jason, Ruhl, Greg, Karnik, Tanay, Borkar, Shekhar Y., De, Vivek, Keshavarzi, Ali

“…As silicon technology scales, the possibility of fabricating dense memories is of great interest, particularly if the solution has low to no additional process…”
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A 256-Kb Dual- SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor by Khellah, M., Somasekhar, D., Ye, Y., Nam Sung Kim, Howard, J., Ruhl, G., Sunna, M., Tschanz, J., Borkar, N., Hamzaoglu, F., Pandya, G., Farhang, A., Zhang, K., De, V.

“…This paper addresses the stability problem of SRAM cells used in dense last level caches (LLCs). In order for the LLC not to limit the minimum voltage at which…”
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A 256-Kb dual-VCC SRAM building block in 65-nm CMOS process with actively clamped sleep transistor by KHELLAH, Muhammad, SOMASEKHAR, Dinesh, PANDYA, Gunjan, FARHANG, Ali, ZHANG, Kevin, DE, Vivek, YIBIN YE, NAM SUNG KIM, HOWARD, Jason, RUHL, Greg, SUNNA, Murad, TSCHANZ, James, BORKAR, Nitin, HAMZAOGLU, Fatih

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Braced caisson minimal structure for water depths up to 260 ft by Ruhl, Greg

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A 5 GHz floating point multiply-accumulator in 90 nm dual VT CMOS by Vangal, Sriram, Hoskote, Yatin, Somasekhar, Dinesh, Erraguntla, Vasantha, Howard, Jason, Ruhl, Greg, Veeramachaneni, Venkat, Finan, David, Mathew, Sanu, Borkar, Nitin

“…A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and…”
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