Search Results - "Rower, Thomas"

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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Design and verification of a stack processor virtual component by Stadler, M., Thalmann, M., Rower, T., Kaeslin, H., Felber, N., Fichtner, W.

“…Hardware and software codesign and flexibility requirements often necessitate embedded application-specific instruction-set processors in system-on-chip…”
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Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor by Stadler, M., Rower, T., Kaeslin, H., Felber, N., Fichtner, W., Thalmann, M.

“…Scalability and customization properties of IP modules demand for new approaches in functional verification. We present a novel simulation-based solution for…”
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A single-chip solution for an ADM-1/TMX-1 SDH telecommunication node element by Thalmann, M., Stadler, M., Rower, T., Felber, N., Fichtner, W.

“…A novel architecture for an ultra compact Add-Drop/Terminal-Multiplexer for Synchronous Digital Hierarchy (SDH) telecommunication networks is reported. This…”
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Intellectual property module of a highly parametrizable embedded stack processor by Rower, T., Stadler, M., Thalmann, M., Felber, N., Kaeslin, H., Fichtner, W.

“…Customizable microprocessors pose numerous design problems that arise from application-specific needs for data operations, word widths, storage capacities, and…”
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A parametrizable hybrid stack-register processor as soft intellectual property module by Luthi, P., Rower, T., Stadler, M., Forrer, D., Moscibroda, S., Felber, N., Kaeslin, H., Fichtner, W.

“…Hardware/software co-design usually encounters serious problems to guarantee strong real-time constraints while serving many interrupt routines. We present an…”
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