Search Results - "Rovedo, N"

Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs by Nayfeh, H.M., Rovedo, N., Bryant, A., Narasimha, S., Kumar, A., Xiaojun Yu, Ning Su, Kumar, A., Sleight, J.W., Robison, R.R., Rausch, W., Mallela, H., Freeman, G.

“…Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric…”
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The effects of fluorine on parametrics and reliability in a 0.18-μm 3.5/6.8 nm dual gate oxide CMOS technology by Hook, T B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

“…Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in…”
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A robust 45 nm gate-length CMOSFET for 90 nm Hi-speed technology by Lim, K.Y., Chan, V., Rengarajan, R., Lee, H.K., Rovedo, N., Lim, E.H., Yang, S., Jamin, F., Nguyen, P., Lin, W., Lai, C.W., Teh, Y.W., Lee, J., Kim, L., Luo, Z., Ng, H., Sudijono, J., Wann, C., Yang, I.

“…We have developed a robust 45 nm gate-length CMOSFET for 90 nm node high performance application. Aggressive gate length and gate dielectric scaling along with…”
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On the integration of CMOS with hybrid crystal orientations by Yang, M., Chan, V., Ku, S.H., Ieong, M., Shi, L., Chan, K.K., Murthy, C.S., Mo, R.T., Yang, H.S., Lehner, E.A., Surpris, Y., Jamin, F.F., Oldiges, P., Zhang, Y., To, B.N., Holt, J.R., Steen, S.E., Chudzik, M.P., Fried, D.M., Bernstein, K., Zhu, H., Sung, C.Y., Ott, J.A., Boyd, D.C., Rovedo, N.

“…Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring…”
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Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates by Qiqing Ouyang, Min Yang, Holt, J., Panda, S., Huajie Chen, Utomo, H., Fischetti, M., Rovedo, N., Jinghong Li, Klymko, N., Wildman, H., Kanarsky, T., Costrini, G., Fried, D.M., Bryant, A., Ott, J.A., Meikei Ieong, Chun-Yung Sung

“…CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation…”
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A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance by Buti, T.N., Ogura, S., Rovedo, N., Tobimatsu, K.

“…An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the…”
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Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability by Lim, K.Y., Chan, V., Rengarajan, R., Lee, H.K., Rovedo, N., Lim, E.H., Yang, S., Jamin, F., Nguyen, P., Lin, W., Lai, C.W., Teh, Y.W., Lee, J., Kim, L., Luo, Z., Ng, H., Sudijono, J., Wann, C., Yang, I.

“…In this paper, a study on middle-of-line (MOL) process on transistor performance and reliability was presented based on 300mm experimental data. The major MOL…”
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Blanket SMT With In Situ N2 Plasma Treatment on the \langle \hbox \rangle Wafer for the Low-Cost Low-Power Technology Application by Jun Yuan, Chan, V., Rovedo, N., Sardesai, V., Kanike, N., Varadarajan, V., Yu, M., Jong Ho Yang, Jeong, Y.K., Kwon, O.S., Belyansky, M.P., Eller, M., Yong Meng Lee, Cave, N., Huiling Shang, Ying Li, Divakaruni, R.

“…PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with ?100? orientation has been observed, and the degradation…”
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Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy by Yaocheng Liu, Gluschenkov, O., Jinghong Li, Madan, A., Ozcan, A., Byeong Kim, Dyer, T., Chakravarti, A., Chan, K., Lavoie, C., Popova, I., Pinto, T., Rovedo, N., Zhijiong Luo, Loesing, R., Henson, W., Ken Rim

“…Current drive enhancement is demonstrated in sub-40 nm NFETs with strained silicon carbon (Si:C) source and drain using a novel solid-phase epitaxy (SPE)…”
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Blanket SMT With In Situ N2 Plasma Treatment on the langle hbox 100 rangle Wafer for the Low-Cost Low-Power Technology Application by Yuan, Jun, Chan, V, Rovedo, N, Sardesai, V, Kanike, N, Varadarajan, V, Yu, M, Ho Yang, Jong, Jeong, Y K, Kwon, O S, Belyansky, M P, Eller, M, Meng Lee, Yong, Cave, N, Shang, Huiling, Li, Ying, Divakaruni, R

“…PMOS degradation with the blanket-stress-memory-technique (SMT) nitride layer on the (100) wafer with ?100? orientation has been observed, and the degradation…”
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Blanket SMT With In Situ N2 Plasma Treatment on the (100) Wafer for the Low-Cost Low-Power Technology Application by JUN YUAN, CHAN, Victor, BELYANSKY, Michael P, ELLER, Manfred, YONG MENG LEE, CAVE, Nigel, HUILING SHANG, YING LI, DIVAKARUNI, Rama, ROVEDO, Nivo, SARDESAI, Viraj, KANIKE, Narasimhulu, VARADARAJAN, Vidya, YU, Mickey, JONG HO YANG, JEONG, Y. K, SUNG KWON, O

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Scalability and biasing strategy for CMOS with active well bias by Shih-Fen Huang, Wann, C., Yu-Shyang Huang, Chih-Yung Lin, Schafbauer, T., Shui-Ming Cheng, Yao-Ching Cheng, Vietzke, D., Eller, M., Chuan Lin, Quiyi Ye, Rovedo, N., Biesemans, S., Nguyen, P., Dennard, R., Bomy Chen

“…We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active…”
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Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration by Hook, Terence B., Bolam, Ronald, Clark, William, Burnham, Jay, Rovedo, Nivo, Schutz, Laura

“…In these experiments, we explored various methods of nitridation of thermal oxide. Rapid thermal oxidation (RTO), rapid thermal oxidation with nitric oxide…”
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A robust 45nm gate-length CMOSFET for 90nm Hi-speed technology by Lim, K.Y., Chan, V., Rengarajan, R., Lee, H.K., Rovedo, N., Lim, E.H., Yang, S., Jamin, F., Nguyen, P., Lin, W., Lai, C.W., Teh, Y.W., Lee, J., Kim, L., Luo, Z., Ng, H., Sudijono, J., Wann, C., Yang, I.

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The effects of fluorine on parametrics and reliability in a0.18-mu m 3.5/6.8 nm dual gate oxide CMOS technology by Hook, T B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

“…Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in…”
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The effects of fluorine on parametrics and reliability in a 0.18-[mu]m 3.5/6.8 nm dual gate oxide CMOS technology by Hook, T.B, Adler, E, Guarin, F, Lukaitis, J, Rovedo, N, Schruefer, K

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The effects of fluorine on parametrics and reliability in a 0.18-/spl mu/m 3.5/6.8 nm dual gate oxide CMOS technology by Hook, T.B., Adler, E., Guarin, F., Lukaitis, J., Rovedo, N., Schruefer, K.

“…Fluorine was introduced into the gate oxide by implantation at various doses into the gate polysilicon. After complete processing, the fluorine remaining in…”
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High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology by Luo, Z., Rovedo, N., Ong, S., Phoong, B., Eller, M., Utomo, H., Ryou, C., Wang, H., Stierstorfer, R., Clevenger, L., Kim, S., Toomey, J., Sciacca, D., Li, J., Wille, W., Zhao, L., Teo, L., Dyer, T., Fang, S., Yan, J., Kwon, O., Park, D., Holt, J., Han, J., Chan, V., Yuan, J., Kebede, T., Lee, H., Kim, S., Lee, S., Vayshenker, A., Yang, Z., Tian, C., Ng, H., Shang, H., Hierlemann, M., Ku, J., Sudijono, J., Ieong, M.

“…An aggressively scaled high performance 45nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through…”
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Mechanism of Threshold Voltage Shift (Δ V th ) Caused by Negative Bias Temperature Instability (NBTI) in Deep Submicron pMOSFETs by Liu, Chuan-Hsi, Lee, Ming T., Lin, Chih-Yung, Chen, Jenkon, Loh, Y. T., Liou, Fu-Tai, Schruefer, Klaus, Katsetos, Anastasios A., Yang, Zhijian, Rovedo, Nivo, Hook, Terence B., Wann, Clement, Chen, Tze-Chiang

“…The physical mechanism responsible for negative bias temperature instability, which is basic to the minimization of this degradation mode, is investigated, and…”
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A half micron MOSFET using double implanted LDD by Ogura, S., Codella, C.F., Rovedo, N., Shepard, J.F., Riseman, J.

“…Double-implanted LDD, which consists of self-aligned p pockets below the n regions in LDD, is introduced to improve both breakdown and short channel effects…”
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