Search Results - "Roh, Tae Moon"

Demonstration of Reconfigurable FET and Logic Gates on Epitaxial Lateral Overgrowth Silicon Platform by Lee, Seong Hyun, Kim, Sang Hoon, Jung, Sungyeop, Park, Jeong Woo, Roh, Tae Moon, Lee, Wangjoo, Suh, Dongwoo

“…We developed a novel technique, selective epitaxial lateral overgrowth (ELO), to fabricate a local but sufficiently large silicon-on-insulator (SOI) platform…”
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Analysis of temporal carrier build‐up in reconfigurable field‐effect transistor by Park, Jeong Woo, Lee, Seong Hyun, Kim, Sang Hoon, Roh, Tae Moon, Suh, Dongwoo

“…Based on the analysis of the carrier density change of a symmetric gate reconfigurable field‐effect transistor that can operate p‐ or n‐type transistors in an…”
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High-voltage power integrated circuit technology using SOI for driving plasma display panels by Jongdae Kim, Tae Moon Roh, Sang-Gi Kim, Song, Q.S., Dae Woo Lee, Jin-Gun Koo, Kyong-IK Cho, Dong Sung Ma

“…A new high-voltage (HV) power IC technology using high-performance p-LDMOS transistors and an excellent dielectric isolation technology has been proposed to…”
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Characterization of Reconfigurable FETs Fabricated on Si Epilayer on SiO2 by Hyun Lee, Seong, Kim, Sang-Hoon, Woo Park, Jeong, Moon Roh, Tae, Jung, Sungyeop, Suh, Dongwoo

“…We report characteristics of reconfigurable field effect transistors (FETs) fabricated on locally grown Si epilayer on amorphous SiO 2 . The present devices…”
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Optical characteristics of silicon semiconductor bridges under high current density conditions by Jongdae Kim, Tae Moon Roh, Kyoung-Ik Cho, Jungling, K.C.

“…The optical emission spectra (180-700 nm) of plasma produced by a semiconductor bridge (SCB) with aluminum or tungsten electrodes have been measured and…”
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A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing by Kim, Jongdae, Roh, Tae Moon, Kim, Sang-Gi, Park, Il-Yong, Lee, Bun

“…A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher…”
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A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture by Jeon, Young-Deuk, Nam, Jae-Won, Kim, Kwi-Dong, Roh, Tae Moon, Kwon, Jong-Kee

“…This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed…”
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A highly reliable trench DMOSFET employing self-align technique and hydrogen annealing by Kim, Jongdae, Roh, Tae Moon, Kim, Sang-Gi, Lee, Jin Ho, Cho, Kyoung-Ik, Kang, Young Il

“…A novel process technique for fabricating trench double diffused MOSFETs (DMOSFET) using three mask layers is realized in order to obtain cost-effective…”
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A novel simplified process for fabricating a very high density p-channel trench gate power MOSFET by Nam, Kee Soo, Lee, Ju Wook, Kim, Sang-Gi, Roh, Tae Moon, Park, Hoon Soo, Koo, Jin Gun, Cho, Kyung Ik

“…A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is…”
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Fast human detection using selective block-based HOG-LBP by Won-Jae Park, Dae-Hwan Kim, Suryanto, S., Chun-Gi Lyuh, Tae Moon Roh, Sung-Jea Ko

“…We propose a speed up method for the Histograms of Oriented Gradients - Local Binary Pattern (HOG-LBP) based pedestrian detector. Our method is based on the…”
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Rare-earth gate oxides for GaAs MOSFET application by Kwon, Kwang-Ho, Yang, Jun-Kyu, Park, Hyung-Ho, Kim, Jongdae, Roh, Tae Moon

“…Rare-earth oxide films for gate dielectric on n-GaAs have been investigated. The oxide films were e-beam evaporated on S-passivated GaAs, considering…”
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A novel automatic white balance for image stitching on mobile devices by Seung-Kyun Kim, Seung-Won Jung, Kang-A Choi, Tae Moon Roh, Sung-Jea Ko

“…When several images are stitched into a panorama, the illumination difference across input images remains as a major problem. To maintain the color constancy…”
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Behavior of trench surface by H2 annealing for reliable trench gate oxide by KIM, Sang-Gi, TAE MOON ROH, KIM, Jongdae, IL YONG PARK, JU WOOK LEE, JIN GUN KOO, BAE, In-Ho, KYOUNG IK CHO

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Predictive model of a reduced surface field p-LDMOSFET using neural network by Kim, Byunghwhan, Kim, Sungmo, Lee, Dae Woo, Roh, Tae Moon, Kim, Jongdae

“…Due to complex dynamics, it has been extremely difficult to model high power devices. A predictive model is constructed by using a backpropagation neural…”
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Binary-Truncated CDMA-Based On-Chip Network by Chun, Ik-Jae, Roh, Tae-Moon, Kim, Bo-Gwan

“…In this paper we present a new communication network for on-chip interconnection. The network concentrates on small size communication link, non blocking…”
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In situ implementation of silicon epitaxial layer on amorphous SiO2 using reduced-pressure chemical vapor deposition by Kim, Sang-Hoon, Lee, Seong Hyun, Park, Jeong-Woo, Roh, Tae Moon, Suh, Dongwoo

“…•A silicon epilayer is grown on amorphous SiO2 by lateral overgrowth mechanism, which shows excellent crystalline quality from SEM and HRTEM analyses. With the…”
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A simple and accurate MESFET channel-current model including bias-dependent dispersion and thermal phenomena by Roh, Tae M, Kim, Youngsik, Suh, Youngsuk, Park, Wee S, Kim, Bumman

“…A new channel-current model of GaAs MESFET suitable for applications to microwave computer-aided design (CAD) has been developed. This model includes the…”
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Effects of buffer layer structure on polysilicon buffer LOCOS for the isolation of submicron silicon devices by Lee, Jong-Ho, Lyu, Jong-Son, Roh, Tae Moon, Kim, Bo Woo

“…The effects of a buffer layer structure on polysilicon buffered LOCOS were shown and analyzed. Sample wafers are classified into four groups to show the effect…”
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Electrical properties of ultrathin oxide grown by high pressure oxidation and N2O nitridation for ULSI device applications by Roh, Tae Moon, Lee, Dae Woo, Kim, Jongdae, Koo, Jin Gun, Nam, Kee Soo, Lee, Duk-Dong

“…For the first time, the feasibility of ultrathin oxides grown by high pressure oxidation (HIPOX) technology in O 2 ambient and nitrided in N 2 O ambient with…”
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A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS by Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon

“…This paper presents a 12-bit 100-MS/s pipeline analog-to-digital converter (ADC) in a 45-nm CMOS technology. The low-voltage circuit techniques and a careful…”
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