Search Results - "Refan, F."

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  1. 1
    "Plug & Test" at System Level via Testable TLM Primitives

    "Plug & Test" at System Level via Testable TLM Primitives by Alemzadeh, H., Di Carlo, S., Refan, F., Prinetto, P., Navabi, Z.

    Published in 2008 IEEE International Test Conference (01-10-2008)
    “…With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a…”
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  2. 2
    A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages

    A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages by Aminlou, A., Refan, F., Hashemi, M.R., Fatemi, O., Safari, S.

    “…Discrete wavelet transform (DWT) is increasingly recognized in image/video compression standards, as indicated by its use in JPEG2000. The lifting scheme…”
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  3. 3
    Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform

    Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform by Aminlou, A., Refan, F., Hashemi, M.R., Fatemi, O.

    “…Implementing the discrete wavelet transform, which is being increasingly recognized in image/video compression standards, in hardware is highly area-consuming…”
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  4. 4
    A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform

    A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform by Aminlou, A., Refan, F., Homayouni, M., Fatemi, O., Hashemi, M.R.

    “…Discrete wavelet transform (DWT) is increasingly recognized in image/video compression standards, as indicated by its use in JPEG2000. The lifting scheme…”
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  5. 5
    Reliability in Application Specific Mesh-Based NoC Architectures

    Reliability in Application Specific Mesh-Based NoC Architectures by Refan, F., Alemzadeh, H., Safari, S., Prinetto, P., Navabi, Z.

    “…Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield…”
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  6. 6
    An IEEE 1500 compatible wrapper architecture for testing cores at transaction level

    An IEEE 1500 compatible wrapper architecture for testing cores at transaction level by Refan, F, Prinetto, P, Navabi, Z

    “…With the evolution of Electronic System Level (ESL) design methodologies, Transaction Level Modeling (TLM) is regarded as the next step in the direction of…”
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  7. 7
    Application specific configuration of a fault-tolerant NoC architecture

    Application specific configuration of a fault-tolerant NoC architecture by Refan, F., Kabiri, P., Alemzadeh, H., Prinetto, P., Navabi, Z.

    “…This paper discusses the configuration of a fault-tolerant mesh-based NoC architecture. In this architecture, spare links provide a mechanism for rerouting…”
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