Area-, Power-, and Delay-Optimized 2D FIR Filter Architecture for Image Processing Applications

The 2D finite impulse response filters are efficient and are of low complexity, and they are often used for image restoration, image enhancement, and denoising applications. The 2D FIR filter architecture usually includes multipliers implemented using a network of adders/subtractors and shifters, wh...

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Bibliographic Details
Published in:	Circuits, systems, and signal processing Vol. 42; no. 2; pp. 780 - 800
Main Authors:	Kumar, Gundugonti Kishore, Akurati, Ravi Raja, Reddy, Venkata Hanuma Prasad, Cheemalakonda, Soumica, Chagarlamudi, Sudeeksha, Dasari, Bhasita, Shaik, Sameera Sulthana
Format:	Journal Article
Language:	English
Published:	New York Springer US 01-02-2023 Springer Nature B.V
Subjects:	Algorithms Circuits and Systems Coefficients Critical path Delay Design optimization Electrical Engineering Electronics and Microelectronics Engineering Field programmable gate arrays FIR filters Image enhancement Image filters Image processing Image restoration Instrumentation Kernels Multiplication & division Optimization Power consumption Signal processing Signal,Image and Speech Processing 2D FIR filter Radix-2r multiplication ASIC Hybrid II architecture RTL FPGA
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Summary:	The 2D finite impulse response filters are efficient and are of low complexity, and they are often used for image restoration, image enhancement, and denoising applications. The 2D FIR filter architecture usually includes multipliers implemented using a network of adders/subtractors and shifters, which can be further optimized. Radix-2r multiplication is used for area, power, and delay optimization in the proposed research work. The symmetric 2D FIR filter coefficients considered in the present work are obtained using the modified Park–McClellan transformation method and are optimized using radix-2r multiplication. These coefficients are implemented using fully direct and hybrid II architectures and in gate-level Verilog HDL. The optimized filter’s efficacy is checked using Intel DSP Builder and synthesized using the Cadence RTL compiler. The results of both FPGA and ASIC synthesis results are compared to previous studies. The area, power, and delay results show that the proposed filter occupies less area, consumes less power, and has less delay than existing optimizations. Additionally, this optimization approach is implemented on standard coefficients of 3 × 3 , 5 × 5 , and 7 × 7 kernels. The FPGA results of these kernels are also compared with previous studies.
ISSN:	0278-081X 1531-5878
DOI:	10.1007/s00034-022-02232-y