Search Results - "Rassekh, Amin"
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Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Published in IEEE journal of the Electron Devices Society (2020)“…In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is…”
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2
Tunneling Current Through a Double Quantum Dots System
Published in IEEE access (2022)“…Electrostatically confined quantum dots in semiconductors hold the promise to achieve high scalability and reliability levels for practical implementation of…”
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3
A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET
Published in Journal of computational electronics (01-06-2020)“…We present a detailed study on the n -channel single-gate junctionless transistor (JLT) at the 10 - nm node. We investigate the influence of its structural…”
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4
Communication at the Speed of Light (CaSoL): A New Paradigm for Designing Global Wires
Published in IEEE transactions on electron devices (01-08-2019)“…In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on…”
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5
Nonhysteretic Condition in Negative Capacitance Junctionless FETs
Published in IEEE transactions on electron devices (01-02-2022)“…This article analyzes the design space stability of negative capacitance double-gate junctionless field-effect transistors (NCDG JLFETs). Using analytical…”
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6
Design space of quantum dot spin qubits
Published in Physica. B, Condensed matter (01-10-2023)“…Solid-state qubits can be implemented with electrostatically confined quantum dots in semiconductors, allowing gate voltages to independently control the…”
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7
Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects
Published in IEEE transactions on electron devices (01-11-2019)“…In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed…”
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8
Design Space of Negative Capacitance in FETs
Published in IEEE transactions on nanotechnology (2022)“…Relying on the previously developed charge-based approaches, this paper presents a physics-based design space of negative capacitance in double-gate and bulk…”
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9
An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction
Published in IEEE electron device letters (01-04-2020)“…This experimental study investigates a novel multi-functional one dimensional-two dimensional (1D-2D) heterojunction made of two different band-gap…”
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10
Simplified EPFL HEMT Model
Published in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) (09-09-2024)“…This paper introduces a simplified and design-oriented version of the EPFL HEMT model [1], focusing on the normalized transconductance-to-current…”
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Conference Proceeding -
11
An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe 2 Hetero-Junction
Published in IEEE electron device letters (01-04-2020)Get full text
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12
Simplified EPFL GaN HEMT Model
Published 05-09-2024“…This paper introduces a simplified and design-oriented version of the EPFL HEMT model [1], focusing on the normalized transconductance-to-current…”
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Journal Article -
13
Non-Hysteretic Condition in Negative Capacitance Junctionless FETs
Published 18-08-2021“…This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a…”
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Journal Article -
14
GaN-on-Porous Silicon for RF Applications
Published in 2023 53rd European Microwave Conference (EuMC) (19-09-2023)“…Gallium nitride (GaN) is a promising semiconductor for RF and high-power applications. However, its large-scale industrialization is hindered by several…”
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Conference Proceeding -
15
Negative Capacitance DG Junctionless FETs: A Charge-based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Published 03-03-2020“…In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed…”
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Journal Article -
16
Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects
Published 18-09-2019“…In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a…”
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Journal Article