A 4-bit 2ps Resolution Time-to-Digital Converter Utilizing Multi-Path Delay Line for ADPLL

A low power high-resolution time-to-digital converter (TDC) is presented. It utilizes a novel multi-path delay line to achieve a sub-gate delay resolution while consuming low power. An offset calibration scheme is also introduced to cancel offsets of both the delay line and the flip-flop. The propos...

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Bibliographic Details
Published in:	2019 31st International Conference on Microelectronics (ICM) pp. 210 - 213
Main Authors:	Hassan, Omar. H., Rashed, Kareem R., Hussien, Faisal A., Aboudina, Mohamed M.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-12-2019
Subjects:	ADPLL Calibration Clocks Delay lines Delays high resolution Inverters low power multi-path offset calibration Power demand Time-to-digital converter Tin
Online Access:	Get full text
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Summary:	A low power high-resolution time-to-digital converter (TDC) is presented. It utilizes a novel multi-path delay line to achieve a sub-gate delay resolution while consuming low power. An offset calibration scheme is also introduced to cancel offsets of both the delay line and the flip-flop. The proposed TDC is designed and simulated in 40nm technology. It achieves 2ps resolution and 1.5ps peak-integral non-linearity (INL) while drawing 100uA from 1.1V supply at 50MHz input frequency.
DOI:	10.1109/ICM48031.2019.9021937