Search Results - "Rapinoja, T."

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  1. 1
    Multitone Fast Frequency-Hopping Synthesizer for UWB Radio

    Multitone Fast Frequency-Hopping Synthesizer for UWB Radio by Stadius, K., Rapinoja, T., Kaukovuori, J., Ryynanen, J., Halonen, K.A.I.

    “…A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it…”
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  2. 2
    Implementation of all-digital wideband RF frequency synthesizers in 65-nm CMOS technology

    Implementation of all-digital wideband RF frequency synthesizers in 65-nm CMOS technology by Rapinoja, T., Liangge Xu, Stadius, K., Ryynanen, J.

    “…This paper presents two all-digital RF frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked…”
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    Conference Proceeding
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  3. 3
    A digital frequency synthesizer for cognitive radio spectrum sensing applications

    A digital frequency synthesizer for cognitive radio spectrum sensing applications by Rapinoja, T., Stadius, K., Liangge Xu, Lindfors, S., Kaunisto, R., Parssinen, A., Ryynanen, J.

    “…This paper presents a wide-band digital frequency synthesizer architecture targeted for spectrum sensing applications. The proposed digital period synthesizer…”
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  4. 4
    A WiMedia UWB receiver with a synthesizer

    A WiMedia UWB receiver with a synthesizer by Kaltiokallio, M., Saari, V., Rapinoja, T., Stadius, K., Ryynanen, J., Lindfors, S., Halonen, K.

    “…This paper describes a direct-conversion receiver for WiMedia UWB applications. The receiver consists of separate BG1 and BG3 LNAs including a 2.4-GHz notch…”
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  5. 5
    Spectral purity analysis of integer-N PLL

    Spectral purity analysis of integer-N PLL by Rapinoja, T., Stadius, K., Ryynanen, J.

    “…This paper describes a method for mutual phase noise and spurious tones analysis of integer-N phase locked loop (PLL). With this method both contributions of…”
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  6. 6
    Behavioral Model based Simulation Methods for Charge-Pump PLL's

    Behavioral Model based Simulation Methods for Charge-Pump PLL's by Rapinoja, T., Stadius, K., Halonen, K.

    “…This paper discusses the ubiquitous problem of extremely long simulation times in transistor-level design of phase-locked loops (PLL). Methods for reducing…”
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  7. 7
    A Low-Power Phase-Locked Loop for UWB Applications

    A Low-Power Phase-Locked Loop for UWB Applications by Rapinoja, T., Stadius, K., Halonen, K.

    Published in 2006 NORCHIP (01-11-2006)
    “…This paper describes a low-power phase-locked loop (PLL) design for multiband-OFDM UWB synthesizer implemented in a 0.13-mum CMOS process. Three parallel PLLs…”
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