Search Results - "Rajoo, Ranjan"

Modeling Stress in Silicon With TSVs and Its Effect on Mobility by Selvanayagam, C., Xiaowu Zhang, Rajoo, R., Pinjala, D.

“…With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is…”
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A self-contained disposable cartridge microsystem for dengue viral ribonucleic acid extraction by Zhang, Li, Rafei, Siti Mohamed, Xie, Ling, Chew, Michelle Bi-Rong, Ji, Hong Miao, Chen, Yu, Rajoo, Ranjan, Ong, Kian-Leong, Tan, Rosemary, Lau, Suk-Hiang, Chow, Vincent T.K., Heng, Chew-Kiat, Teo, Keng-Hwa, Kang, Tae Goo

“…A self-contained disposable polydimethylsiloxane (PDMS) cartridge was developed for the extraction of dengue viral ribonucleic acid (RNA) in solid phase. The…”
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Comparison of Mechanical Properties of Nickel-Palladium Plated and Tin-Plated Copper Leadframe Material at Elevated Temperatures by Zhu, Xintong, Rajoo, Ranjan, Nistala, Ramesh Rao, Mo, Zhi Qiang

“…In this paper the mechanical properties of Copper-based (Cu) leadframe with Tin (Sn) and Nickel-Palladium (NiPd) finishing are compared by using…”
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Material characterization for nano wafer level packaging application by Sau Koh, Ranjan Rajoo, Rao Tummala, Ashok Saxena, Kuo Tsing Tsai

“…As the feature size of integrated circuit (IC) packages needs to be decreased significantly, computational methods in conjunction with experimental data have…”
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Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultrathin Device by Xiaowu Zhang, Rajoo, R., Selvanayagam, C. S., Kumar, A., Rao, V. S., Khan, N., Kripesh, V., Lau, J. H., Dim-Lee Kwong, Sundaram, V., Tummala, R. R.

“…Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous…”
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Impact of High Temperature Storage for Prolonged Duration on Cu Leadframe Material Properties for Automotive Applications by Zhu, Xintong, Rajoo, Ranjan, Yip, Kim Hong, Ang, Poh Chuan, Nistala, Ramesh Rao, Mo, Zhi Qiang

“…Copper-based leadframe material with Tin (Sn) and Nickel-Palladium (NiPd) finishing are studied in this work. The samples are subjected to high temperature…”
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Dicing Blade Characterization Using Nano-indentation by Zhu, Xintong, Rajoo, Ranjan, Nistala, Ramesh Rao, Chan, Kai Chong, Mo, Zhi Qiang

“…In this paper, the widely used nano-indentation technique is employed to characterize the mechanical properties of dicing blade. The dicing blade is a…”
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Process and Reliability of Embedded Micro-Wafer-Level Package (EMWLP) Using Low Cure Temperature Dielectric Material by Rao, V. S., Sekhar, V. N., Ho Soon Wee, Rajoo, R., Sharma, G., Lim Ying Ying, Damaruganath, P.

“…In this paper, we present the evaluation results of low cure temperature (less than 200°C) dielectric materials (LCTDMs) in terms of processability and…”
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Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages by Sharma, G, Rao, V S, Kumar, A, Lim Ying Ying, Khong Chee Houe, Lim, S, Sekhar, V N, Rajoo, R, Kripesh, V, Lau, J H

“…Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional…”
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Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs) by Xiaowu Zhang, Rajoo, R, Selvanayagam, C S, Premachandran, C S, Won Kyoung Choi, Soon Wee Ho, Siong Chiew Ong, Ling Xie, Pinjala, D, Dim-Lee Kwong, Yee Mong Khoo, Shan Gao

“…Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component…”
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Development of process modeling methodology for flip chip on flex interconnections with non-conductive adhesives by Zhang, Xiaowu, Wong, E.H., Rajoo, Ranjan, Iyer, Mahadevan K., Caers, J.F.J.M., Zhao, X.J.

“…This paper presents a comprehensive methodology to model the assembly process of flip chip on flex interconnections with non-conductive adhesives (NCAs). The…”
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Moisture characteristics of wafer level compression molding compounds by Rajoo, Ranjan, Xiaowu Zhang

“…This paper presents moisture characteristics of 10 wafer level compression molding compounds manufactured by 6 leading manufacturers. Moisture absorption test…”
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Swelling and time-dependent subcritical debonding of underfill during temperature-humidity aging of flip chip packages by Wong, E.H., Rajoo, R., Lim, T.B., Yui-Wing Mai

“…Stress corrosion cracking and the associated time-dependent subcritical debonding of the underfill-die interface is believed to be responsible for a large…”
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Enabling fine pitch Cu & Ag alloy wire bond assessment for 28nm ultra low-k structure by Beleran, John D., Milanes, Ninoy, Mehta, Gaurav, Suthiwongsunthorn, Nathapong, Rajoo, Ranjan, Chan Kai Chong

“…The use of copper wire in IC packaging has been growing steadily driven by cost effectiveness. However, there are concerns and issues that prevent or delay…”
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Design and fabrication of embedded passives on thin flexible substrates and reliability evaluation of passives performance by Ying Ying Lim, Rajoo, Ranjan, Ser Choong Chong

“…Recent trends favour the widespread adoption of RFID technology for supply chain and retail applications. To be economically viable, the tags have to be…”
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Study on low-cost QFN packages for high-frequency applications by Boyu Zheng, Cubillo, J. R., Katti, G., Cheng Jin, Rajoo, R., Kai Chong Chan

“…Quad flat no-lead (QFN) packages have found wide applications in RF and high-speed digital systems. The purpose of this paper is to study high-frequency…”
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Design and reliability analysis of pyramidal shape 3-layer stacked TSV die package by Che, F. X., Chai, T. C., Lim, S. P. S., Rajoo, R., Xiaowu Zhang

“…In this work, the reliability of a pyramidal shape 3-layer stacked TSV die package has been studied by experiments and finite element analysis (FEA). The…”
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Embedded wafer level packages with laterally placed and vertically stacked thin dies by Sharma, G., Rao, V.S., Kumar, A., Su, N., Lim Ying Ying, Khong Chee Houe, Lim, S., Sekhar, V.N., Rajoo, R., Kripesh, V., Lau, J.H.

“…Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin…”
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A low stress bond pad design optimization of low temperature solder interconnections on TSVs for MEMS applications by Xiaowu Zhang, Rajoo, R., Che, F. X., Selvanayagam, C. S., Choi, W. K., Shan Gao, Lo, G. Q., Kwong, D.-L

“…In new applications (such as MEMS, bio-MEMS), vertical integration requires a low processing temperature below 200°C to bond these devices without degrading…”
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Design and Development of Fine Pitch Copper/Low-K Wafer Level Package by Rao, Vempati Srinivasa, Xiaowu Zhang, Ho Soon Wee, Rajoo, Ranjan, Premachandran, C S, Kripesh, Vaidyanathan, Seung Wook Yoon, Lau, John H

“…Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch,…”
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