Search Results - "Rafferty, C.S."

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  1. 1

    Device-level simulation of wave propagation along metal-insulator-semiconductor interconnects by Gaofeng Wang, Dutton, R.W., Rafferty, C.S.

    “…A device-level simulation is presented for studying wave propagation along metal-insulator-semiconductor interconnects. A set of nonlinear equations is first…”
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    Journal Article
  2. 2

    Use of transient enhanced diffusion to tailor boron out-diffusion by Vuong, H.-H., Xie, Y.-H., Frei, M.R., Hobler, G., Pelaz, L., Rafferty, C.S.

    Published in IEEE transactions on electron devices (01-07-2000)
    “…We report experimental results demonstrating the use of transient enhanced diffusion (TED) caused by silicon implant for "tuning" boron out-diffusion. The…”
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    Journal Article
  3. 3

    Effects of oxide interface traps and transient enhanced diffusion on the process modeling of PMOS devices by Vuong, H.-H., Rafferty, C.S., Eshraghi, S.A., Lentz, J.L., Zeitzoff, P.M., Pinto, M.R., Hillenius, S.J.

    Published in IEEE transactions on electron devices (01-07-1996)
    “…We present a model which simulates the trapping of arsenic and boron dopants at the silicon-silicon dioxide interface, and demonstrate that this model gives…”
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    Journal Article
  4. 4

    Kinetic Monte Carlo simulations: an accurate bridge between ab initio calculations and standard process experimental data by Jaraiz, M, Rubio, E, Castrillo, P, Pelaz, L, Bailon, L, Barbolla, J, Gilmer, G.H, Rafferty, C.S

    “…Kinetic Monte Carlo (KMC) atomistic process simulations mimic the jumps and interactions of individual atoms, based on jump rates derived from ab initio…”
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    Journal Article
  5. 5

    Ultrashallow junctions for ULSI using As/sub 2//sup +/ implantation and rapid thermal anneal by Park, B.G., Bokor, J., Luftman, H.S., Rafferty, C.S., Pinto, M.R.

    Published in IEEE electron device letters (01-10-1992)
    “…Using As/sub 2//sup +/ ion implantation and rapid thermal anneal, 40-nm n/sup +/-p junctions are realized. The junction formed with p/sup -/ substrate shows…”
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    Journal Article
  6. 6

    Effective on-current of MOSFETs for large-signal speed consideration by Ng, K.K., Rafferty, C.S., Hong-Ih Cong

    “…To gauge the speed capability of a MOSFET, the maximum saturation on-current is usually quoted as an important parameter. Although the effect of the linear…”
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    Conference Proceeding
  7. 7

    Stable transformation of the yellow fever mosquito, Aedes aegypti, with the Hermes element from the housefly by Jasinskiene, N. (University of California, Irvine.), Coates, C.J, Benedict, M.Q, Cornel, A.J, Rafferty, C.S, James, A.A, Collins, F.H

    “…The mosquito Aedes aegypti is the world's most important vector of yellow fever and dengue viruses. Work is currently in progress to control the transmission…”
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    Journal Article
  8. 8

    Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances by Iwai, H., Pinto, M.R., Rafferty, C.S., Oristian, J.E., Dutton, R.W.

    “…In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor…”
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    Journal Article
  9. 9

    Velocity saturation effect on short-channel MOS transistor capacitance by Iwai, H., Pinto, M.R., Rafferty, C.S., Oristian, J.E., Dutton, R.W.

    Published in IEEE electron device letters (01-03-1985)
    “…To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances…”
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    Journal Article
  10. 10
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    Front-end process simulation by Rafferty, C.S

    Published in Solid-state electronics (01-05-2000)
    “…If the 1980s were the decade in which two-dimensional (2-D) device simulation became widely used for device design, the 1990s saw the widespread adoption of…”
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    Journal Article
  12. 12

    Continuum treatment of spatial correlation in damage annealing by Hobler, G., Pelaz, L., Rafferty, C.S.

    “…The theory of diffusion limited reactions is applied to the recombination of Frenkel pairs in a recoil cascade on top of a background of pairs generated in…”
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    Journal Article
  13. 13

    Quantitative evolution of vacancy-type defects in high-energy ion-implanted Si: Au labeling and the vacancy implanter by Kalyanaraman, R, Haynes, T.E, Yoon, M, Larson, B.C, Jacobson, D.C, Gossmann, H.-J, Rafferty, C.S

    “…In ion implantation related research in Si, the role of interstitial clusters in dopant diffusion is fairly well understood. But there is relatively poor…”
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    Journal Article
  14. 14

    Physical modeling of silicon thermal processing by Rafferty, C.S.

    “…Thermal annealing of dopants implanted in silicon devices causes redistribution of the implanted profiles. Increasingly this redistribution occurs in a…”
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    Conference Proceeding
  15. 15

    Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology by Vuong, H.-H., Eshraghi, S.A., Rafferty, C.S., Hillenius, S.J., Pinto, M.R., Diodato, P.W., Cong, H.-I., Zeitzoff, P.M.

    Published in IEEE transactions on electron devices (01-04-1998)
    “…TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit…”
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    Journal Article
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    Effect of implant damage on the gate oxide thickness by Vuong, H.-H, Bude, J, Baumann, F.H, Evans-Lutterodt, K, Ning, J, Ma, Y, Mcmacken, J, Gossmann, H.-J, Silverman, P, Rafferty, C.S, Hillenius, S.J

    Published in Solid-state electronics (1999)
    “…Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage ( C– V) measurements on…”
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    Journal Article
  18. 18

    Active-gate thin-film transistor by Lifshitz, N., Luryi, S., Pinto, M.R., Rafferty, C.S.

    Published in IEEE electron device letters (01-08-1993)
    “…A thin-film transistor (TFT) with a lightly-doped offset built in the polysilicon gate is proposed. The offset region of the gate acts as a dielectric in the…”
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    Journal Article
  19. 19

    Self-aligned metalization technique for deep-submicron IC's by Lifshitz, N., Pinto, M.R., Rafferty, C.S., Fang, S.C.

    Published in IEEE electron device letters (01-11-1993)
    “…The authors propose a new metalization scheme for deep-submicron IC's that enables fabrication of relatively wide, reliable metal interconnects in a narrow…”
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    Journal Article
  20. 20

    Iterative methods in semiconductor device simulation by Rafferty, C.S., Pinto, M.R., Dutton, R.W.

    Published in IEEE transactions on electron devices (01-10-1985)
    “…This paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of…”
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    Journal Article