Search Results - "RIM, Kern"

A high-speed, high-sensitivity silicon lateral trench photodetector by Min Yang, Kern Rim, Rogers, D.L., Schaub, J.D., Welser, J.J., Kuchta, D.M., Boyd, D.C., Rodier, F., Rabidoux, P.A., Marsh, J.T., Ticknor, A.D., Qingyun Yang, Upham, A., Ramac, S.C.

“…We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed…”
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Scaling of Strain-induced Mobility Enhancements in Advanced CMOS Technology by Rim, K.

“…Mobility enhancement by strain is a critical element in today¿s CMOS technology, and enables continued performance scaling. By modulating fundamental material…”
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Fabrication and analysis of deep submicron strained-Si n-MOSFET's by Rim, K., Hoyt, J.L., Gibbons, J.F.

“…Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub 0.2/ heterostructures. Epitaxial layer structures were designed…”
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Analog/mixed-signal design challenges in 7-nm CMOS and beyond by Loke, Alvin L. S., Yang, Da, Wee, Tin Tin, Holland, Jonathan L., Isakanian, Patrick, Rim, Kern, Yang, Sam, Schneider, Jacob S., Nallapati, Giri, Dundigal, Sreeker, Lakdawala, Hasnain, Amelifard, Behnam, Lee, Chulkyu, McGovern, Betty, Holdaway, Paul S., Kong, Xiaohua, Leary, Burton M.

“…The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology…”
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Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond by Loke, Alvin L. S., Yang, Da, Wee, Tin Tin, Holland, Jonathan L., Isakanian, Patrick, Rim, Kern, Yang, Sam, Schneider, Jacob S., Nallapati, Giri, Dundigal, Sreeker, Lakdawala, Hasnain, Amelifard, Behnam, Lee, Chulkyu, McGovern, Betty, Holdaway, Paul S., Kong, Xiaohua, Leary, Burton M.

“…The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology…”
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Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS by Kim, Keunwoo, Chuang, Ching-Te, Rim, Kern, Joshi, Rajiv V.

“…The device/circuit performance of strained-Si (SS) MOSFETs including strained-Si channel-on-insulator (SSOI) is assessed via a physics-based compact model…”
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Application of silicon-based heterostructures to enhanced mobility metal-oxide-semiconductor field-effect transistors by Rim, Kern

“…As Si CMOS technology scales into the deep submicron regime, new challenges for device design are posed. Reduction of device dimension has been mainly…”
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Compact Modeling Methodology of Strained-Si Channel-on-Insulator (SSOI) MOSFETs by Kim, Keunwoo, Chuang, Ching-Te, Rim, Kern, Cai, Jin, Haensch, Wilfried E.

“…Compact physical models for SSOI MOSFETs are presented. The models consider specific features for strained-Si devices including SSOI such as mobility…”
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Analysis and modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs by Keunwoo Kim, Ching-Te Chuang, Rim, K., Jin Cai, Haensch, W.E.

“…Compact physical models for SSOI MOSFETs are presented. The models consider strained-Si device features including mobility enhancement and band offsets with…”
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Transconductance enhancement in deep submicron strained Si n-MOSFETs by Rim, K., Hoyt, J.L., Gibbons, J.F.

“…We report the first measurements on deep submicron strained-Si n-MOSFETs. In spite of the high channel doping and vertical effective fields, electron mobility…”
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Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS by KIM, Keunwoo, CHUANG, Ching-Te, RIM, Kern, JOSHI, Rajiv V

“…Strained-Si channel devices have recently become of interest for future high-performance applications due to higher carrier mobility and preservation of…”
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