Search Results - "Pude, M"
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1
Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise
Published in IEEE transactions on very large scale integration (VLSI) systems (01-01-2010)“…Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating…”
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Journal Article -
2
Amplifier gain enhancement with positive feedback
Published in 2010 53rd IEEE International Midwest Symposium on Circuits and Systems (01-08-2010)“…The use of positive feedback as a solution to maximum intrinsic gain degradation in scaled technologies is discussed. Criteria for increasing gain while…”
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Conference Proceeding -
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Using positive feedback to overcome gmro limitations in scaled CMOS amplifier design
Published in 2008 51st Midwest Symposium on Circuits and Systems (01-08-2008)“…The use of positive feedback as a solution to intrinsic gain degradation in scaled technologies is discussed. Criteria for increasing gain while keeping the…”
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Conference Proceeding -
4
An analytical propagation delay model with power supply noise effects
Published in 2006 IEEE International Symposium on Circuits and Systems (ISCAS) (2006)“…This paper presents an analytical model for CMOS logic propagation delay which includes the effect of power supply noise. Using the nth power law model of…”
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Conference Proceeding -
5
Maximum intrinsic gain degradation in technology scaling
Published in 2007 International Semiconductor Device Research Symposium (01-12-2007)“…Aggressive device scaling has begun to pose significant problems to the analog design community. For the most part, digital circuitry benefits from the effects…”
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Conference Proceeding