A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing

This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastr...

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Bibliographic Details
Published in:	IEEE journal of solid-state circuits Vol. 45; no. 8; pp. 1615 - 1626
Main Authors:	Rossi, Davide, Campi, Fabio, Spolzino, Simone, Pucillo, Stefano, Guerrieri, Roberto
Format:	Journal Article Conference Proceeding
Language:	English
Published:	New York, NY IEEE 01-08-2010 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Applied sciences Array signal processing Circuit properties Computation Computational modeling Design. Technologies. Operation analysis. Testing Devices Digital Digital circuits Digital signal processors Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Fabrics Field programmable gate arrays globally asynchronous locally synchronous Grains Integrated circuits Integrated circuits by function (including memories and processors) Kernel Mathematical models Microprocessors Network-on-a-chip Network-on-Chip Operating systems Programming profession reconfigurable architectures Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Signal processing Synchronism System-on-a-chip System-on-Chip Transistors Interconnection network Globally asynchronous locally synchronous Die Digital signal processors System-on-Chip Network-on-Chip Network architecture 64 bit Processor Transistor Field programmable gate array System on a chip Synchronization Implementation Granular material Integrated circuit Electric power consumption Signal processing Reconfigurable architectures Digital signal processor Peak power
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Summary:	This paper describes a System on Chip implementation of a reconfigurable digital signal processor. The device is suitable for execution of a wide range of applications exploiting a balanced mix of heterogeneous reconfigurable fabrics merged together by a flexible and efficient communication infrastructure based on a 64-bit Network On Chip. The SoC combines a fine grain embedded FPGA, a mid grain configurable processor and a coarse grain reconfigurable array. An ARM processor featuring a resident operating system is the SoC supervisor, managing communication, synchronization and reconfiguration mechanisms. This computational model enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigurable engines. The SoC has been fabricated in 90-nm technology, the die area being 110 mm 2 ; it integrates 97 million transistors and has a peak power consumption of 2.5 W. In order to demonstrate the proposed computational model and the reconfigurable signal processor capabilities in a real test case, a video surveillance motion detection application was implemented in the SoC. When running this application, the device proved able to deliver 120 GOPS dissipating 1.45 W.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2010.2048149