Search Results - "Proceedings. 21st VLSI Test Symposium, 2003"

Application of Saluja-Karpovsky compactors to test responses with many unknowns by Patel, J.H., Lumetta, S.S., Reddy, S.M.

“…This paper addresses the problem of compacting test responses in the presence of unknowns at the input of the compactor by exploiting the capabilities of…”
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SOC test scheduling using simulated annealing by Wei Zou, Reddy, S.M., Pomeranz, I., Yu Huang

“…We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing…”
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Test data compression using dictionaries with fixed-length indices [SOC testing] by Lei Li, Chakrabarty, K.

“…We present a dictionary-based test data compression approach for reducing test data volume and testing time in SOCs. The proposed method is based on the use of…”
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A reconfigurable shared scan-in architecture by Samaranayake, S., Gizdarski, E., Sitchinava, N., Neuveux, F., Kapur, R., Williams, T.W.

“…In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain…”
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The impact of NoC reuse on the testing of core-based systems by Cota, E., Kreutz, M., Zeferino, C.A., Carro, L., Lubaszewski, M., Susin, A.

“…The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and…”
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Efficient seed utilization for reseeding based compression [logic testing] by Volkerink, E.H., Mitra, S.

“…The conventional LFSR reseeding technique for test data compression generates one test pattern from each LFSR seed. The seed size is determined by the maximum…”
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Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression by Bayraktaroglu, I., Orailoglu, A.

“…A methodology for the determination of decompression hardware that guarantees complete fault coverage for a unified compaction/compression scheme is proposed…”
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BIST-aided scan test - a new method for test cost reduction by Hiraide, T., Kwame Osei Boateng, Konishi, H., Itaya, K., Emori, M., Yamanaka, H., Mochiyama, T.

“…It is common to use ATPG of scan-based design for high fault coverage in LSI testing. However, significant increase in test cost is caused in accordance with…”
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Fault testing for reversible circuits by Patel, K.N., Hayes, J.P., Markov, I.L.

“…Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today's VLSI…”
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Testable design and testing of micro-electro-fluidic arrays by Kerkhoff, H.G., Acar, M.

“…The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is…”
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A circuit level fault model for resistive opens and bridges by Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, Walker, D.M.H.

“…Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a…”
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Testing SoC interconnects for signal integrity using boundary scan by Tehranipour, M.H., Ahmed, N., Nourani, M.

“…As the technology is shrinking toward 50 nm and the working frequency is going into the multi Gigahertz range, the effect of interconnects on functionality and…”
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BIST reseeding with very few seeds by Al-Yamani, A.A., Mitra, S., McCluskey, E.J.

“…Reseeding is used to improve the fault coverage of pseudo-random testing. The seed corresponds to the initial state of the LFSR before filling the scan chain…”
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Automatic configuration generation for FPGA interconnect testing by Tahoori, M.B., Mitra, S.

“…We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The…”
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Analysis and design of optimal combinational compactors [logic test] by Wohl, P., Huisman, L.

“…Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a…”
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Built-in reseeding for serial BIST by Al-Yamani, A.A., McCluskey, E.J.

“…Reseeding is used to improve fault coverage in BIST pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external…”
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Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs by Benware, B.R., Madge, R., Lu, C., Daasch, R.

“…In sub-micron processes, resistive path defects are increasingly contributing to the yield loss and the customer fail pareto. Data has been collected on a…”
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Keynote Address by Fields, J.

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Building yield into systems-on chips for nanometer technologies by Magarshack, P.

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Use of multiple I/sub DDQ/ test metrics for outlier identification by Sabade, S.S., Walker, D.M.H.

“…With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true…”
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