Search Results - "Proceedings of the 31st annual international symposium on Computer architecture"

Transactional Memory Coherence and Consistency by Hammond, Lance, Wong, Vicky, Chen, Mike, Carlstrom, Brian D., Davis, John D., Hertzberg, Ben, Prabhu, Manohar K., Wijaya, Honggo, Kozyrakis, Christos, Olukotun, Kunle

“…In this paper, we propos a new shared memory model: Transactionalmemory Coherence and Consistency (TCC).TCC providesa model in which atomic transactions are…”
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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance by Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

“…A single-ISA heterogeneous multi-core architecture is achip multiprocessor composed of cores of varying size, performance,and complexity. This paper…”
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Adaptive Cache Compression for High-Performance Processors by Alameldeen, Alaa R., Wood, David A.

“…Modern processors use two or more levels ofcache memories to bridge the rising disparity betweenprocessor and memory speeds. Compression canimprove cache…”
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Evaluating the Imagine Stream Architecture by Ahn, Jung Ho, Dally, William J., Khailany, Brucek, Kapasi, Ujval J., Das, Abhishek

“…This paper describes an experimental evaluation of theprototype Imagine stream processor. Imagine [Imagine: Media processing with streams] is a stream…”
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iWatcher: Efficient Architectural Support for Software Debugging by Zhou, Pin, Qin, Feng, Liu, Wei, Zhou, Yuanyuan, Torrellas, Josep

“…Recent impressive performance improvements in computer architecturehave not led to significant gains in ease of debugging.Software debugging often relies on…”
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Physical Register Inlining by Lipasti, Mikko H., Mestan, Brian R., Gunadi, Erika

“…Physical register access time increases the delaybetween scheduling and execution in modern out-of-orderprocessors. As the number of physical registers…”
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Memory Ordering: A Value-Based Approach by Cain, Harold W., Lipasti, Mikko H.

“…Conventional out-of-order processors employ a multi-ported,fully-associative load queue to guarantee correctmemory reference order both within a single thread…”
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X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs by Bairavasundaram, Lakshmi N., Sivathanu, Muthian, Arpaci-Dusseau, Andrea C., Arpaci-Dusseau, Remzi H.

“…RAID storage arrays often possess gigabytes of RAM forcaching disk blocks. Currently, most RAID systems use LRUor LRU-like policies to manage these caches…”
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Exploiting Resonant Behavior to Reduce Inductive Noise by Powell, Michael D., Vijaykumar, T. N.

“…Inductive noise in high-performance microprocessors is a reliabilityissue caused by variations in processor current (di/dt)which are converted to…”
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From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation by Yehia, Sami, Temam, Olivier

“…In this article, we present an approach for improving the performance of sequences of dependent instructions. We observe that many sequences of instructionscan…”
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Use-Based Register Caching with Decoupled Indexing by Butts, J. Adam, Sohi, Gurindar S.

“…Wide, deep pipelines need many physical registersto hold the results of in-flight instructions. Simultaneously,high clock frequencies prohibit using…”
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Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor by Oliver, John, Rao, Ravishankar, Sultana, Paul, Crandall, Jedidiah, Czernikowski, Erik, Jones IV, Leslie W., Franklin, Diana, Akella, Venkatesh, Chong, Frederic T.

“…We present Synchroscalar, a tile-based architecture forembedded processing that is designed to provide the flexibilityof DSPs while approaching the power…”
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Field-testing IMPACT EPIC research results in Itanium 2 by Sias, John W., Ueng, Sain-zee, Kent, Geoff A., Steiner, Ian M., Nystrom, Erik M., Hwu, Wen-mei W.

“…Explicitly-Parallel Instruction Computing (EPIC) providesarchitectural features, including predication and explicitcontrol speculation, intended to enhance the…”
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SMTp: An Architecture for Next-generation Scalable Multi-threading by Chaudhuri, Mainak, Heinrich, Mark

“…We introduce the SMTp architecture-an SMT processoraugmented with a coherence protocol thread context,that together with a standard integrated memory…”
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A Formal Approach to Frequent Energy Adaptations for Multimedia Applications by Hughes, Christopher J., Adve, Sarita V.

“…Much research has recently been done on adapting architecturalresources of general-purpose processors to saveenergy at the cost of increased execution time…”
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Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs by Iyer, Bharath, Srinivasan, Sadagopan, Jacob, Bruce

“…VLIW architecture based DSPs have become widespread due to thecombined benefits of simple hardware and compiler-extractedinstruction-level parallelism…”
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Low-Latency Virtual-Channel Routers for On-Chip Networks by Mullins, Robert, West, Andrew, Moore, Simon

“…The on-chip communication requirements of manysystems are best served through the deployment of a regularchip-wide network. This paper presents the design of…”
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The Case for Lifetime Reliability-Aware Microprocessors by Srinivasan, Jayanth, Adve, Sarita V., Bose, Pradip, Rivers, Jude A.

“…Ensuring long processor lifetimes by limiting failuresdue to wear-out related hard errors is a critical requirementfor all microprocessor manufacturers. We…”
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Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams by Taylor, Michael Bedford, Lee, Walter, Miller, Jason, Wentzlaff, David, Bratt, Ian, Greenwald, Ben, Hoffmann, Henry, Johnson, Paul, Kim, Jason, Psota, James, Saraf, Arvind, Shnidman, Nathan, Strumpen, Volker, Frank, Matt, Amarasinghe, Saman, Agarwal, Anant

“…This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a general-purpose architecture that performswell on a larger class of…”
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A First-Order Superscalar Processor Model by Karkhanis, Tejas S., Smith, James E.

“…A proposed performance model for superscalar processorsconsists of 1) a component that models the relationshipbetween instructions issued per cycle and the…”
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