Search Results - "Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367)"
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PipeRench: a coprocessor for streaming multimedia acceleration
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Future computing workloads will emphasize an architecture's ability to perform relatively simple calculations on massive quantities of mixed-width data. This…”
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2
A performance comparison of contemporary DRAM architectures
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper…”
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3
Simultaneous subordinate microthreading (SSMT)
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Current work in Simultaneous Multithreading provides little benefit to programs that aren't partitioned into threads. We propose Simultaneous Subordinate…”
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4
Effective jump-pointer prefetching for linked data structures
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Current techniques for prefetching linked data structures (LDS) exploit the work available in one loop iteration or recursive call to overlap pointer chasing…”
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Speculation techniques for improving load related instruction scheduling
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-of-order engine, the instruction scheduler is…”
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Selective value prediction
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Value prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction…”
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A scalable front-end architecture for fast instruction delivery
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance…”
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8
A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…This paper presents a novel hardware-based approach for identifying, profiling, and monitoring hot spots in order to support runtime optimization of…”
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9
Multicast snooping: a new coherence method using a multicast address network
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…This paper proposes a new coherence method called "multicast snooping" that dynamically adapts between broadcast snooping and a directory protocol. Multicast…”
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10
Correlated load-address predictors
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute…”
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11
The block-based trace cache
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work…”
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12
Maps: a compiler-managed memory system for Raw machines
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…This paper describes Maps, a compiler managed memory system for Raw architectures. Traditional processors for sequential programs maintain the abstraction of a…”
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13
Storageless value prediction using prior register values
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…This paper presents a technique called register value prediction (RVP) which uses a type of locality called register-value reuse. By predicting that an…”
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14
Scaling application performance on a cache-coherent multiprocessors
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Hardware-coherent, distributed shared address space systems are increasingly successful at moderate scale. However, it is unclear whether, or with how much…”
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15
Commit-Reconcile and Fences (CRF): a new memory model for architects and compiler writers
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…We present a new mechanism-oriented memory model called Commit-Reconcile & Fences (CRF) and define it using algebraic rules. Many existing memory models can be…”
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16
Decoupling local variable accesses in a wide-issue superscalar processor
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large…”
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Memory forwarding: enabling aggressive layout optimizations by guaranteeing the safety of data relocation
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching,…”
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18
Performance of image and video processing with general-purpose processors and media ISA extensions
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without…”
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Memory sharing predictor: the key to a speculative coherent DSM
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately…”
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Area efficient architectures for information integrity in cache memories
Published in Proceedings of the 26th International Symposium on Computer Architecture (Cat. No.99CB36367) (1999)“…Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using…”
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