Search Results - "Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)"

The disjunctive decomposition of logic functions by Bertacco, Valeria, Damiani, Maurizio

“…We present an algorithm for extracting a disjunctive decomposition from the BDD representation of F. The output of the algorithm is a multiple-level netlist…”
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Logic synthesis for large pass transistor circuits by Buch, Premal, Narayan, Amit, Newton, A Richard, Sangiovanni-Vincentelli, A

“…Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. The authors motivate the need for CAD algorithms for PTL…”
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Clock-tree routing realizing a clock-schedule for semi-synchronous circuits by Takahashi, Atsushi, Inoue, Kazunori, Kajitani, Yoji

“…It is known that the clock period can be shorter than the maximum of the signal delays between registers if the clock arrival time to each register is properly…”
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An exact gate decomposition algorithm for low-power technology mapping by Zhou, Hai, Wong, D F

“…With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and…”
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PRIMA: passive reduced-order interconnect macromodeling algorithm by Odabasioglu, Altan, Celik, Mustafa, Pileggi, Lawrence T

“…This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in…”
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A predictive system shutdown method for energy saving of event-driven computation by Hwang, Chi-Hong, Wu, Allen C-H

“…We present a system-level power management technique for power saving of event-driven applications. We present a new predictive system shutdown method to…”
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Efficient coupled noise estimation for on-chip interconnects by Devgan, Anirudh

“…Noise analysis and avoidance is an increasingly critical step in deep submicron design. Ever increasing requirements on performance have led to widespread use…”
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Interconnect design for deep submicron ICs by Cong, Jason, Pan, Zhigang, He, Lei, Koh, Cheng-Kok, Khoo, Kei-Yong

“…Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first…”
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Rectangle-packing-based module placement by Murata, H., Fujiyoshi, K., Nakatake, S., Kajitani, Y.

“…The first and the most critical stage in VLSI layout design is the placement, the background of which is the rectangle packing problem: Given many rectangular…”
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Embedded program timing analysis based on path clustering and architecture classification by Ernst, R, Ye, W

“…Formal program running time verification is an important issue in system design required for performance optimization under "first-time-right" design…”
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A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks by Elfadel, I M, Ling, David D

“…Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic…”
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Reachability analysis using partitioned-ROBDDs by Narayan, Amit, Isles, Adrian J, Jain, Jawahar, Brayton, Robert K, Sangiovanni-Vincentelli, Alberto L

“…We address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of…”
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Global Harmony: coupled noise analysis for full-chip RC interconnect networks by Shepard, K L, Narayanan, V, Elmendorf, P C, Zheng, Gutuan

“…Noise is becoming one of the most important metrics in the design of VLSI systems, certainly of comparable importance to area, timing, and power. In this…”
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Java as a specification language for hardware-software systems by Helaihel, Rachid, Olukotun, Kunle

“…The specification language is a critical component of the hardware-software co-design process since it is used for functional validation and as a starting…”
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A deductive technique for diagnosis of bridging faults by Venkataraman, Srikanth, Fuchs, W Kent

“…A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is…”
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Binary decision diagrams and beyond: enabling technologies for formal verification by Bryant, R.E.

“…Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs…”
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Time-constrained loop pipelining by Sanchez, F., Cortadella, J.

“…This paper addresses the problem of Time-Constrained Loop Pipelining, i.e. given a fixed throughput, finding a schedule of a loop which minimizes resource…”
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MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems by Dick, Robert P, Jha, Niraj K

“…We present a hardware-software co-synthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic…”
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A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists by Tafertshofer, Paul, Ganz, Andreas, Henftling, Manfred

“…The paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and…”
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NRG: global and detailed placement by Sarrafzadeh, Majid, Wang, Maogang

“…We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid…”
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