Search Results - "Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium"

Development of 0.5 and 0.65 mm pitch QFP technology in surface mounting by Liu, J., Tillstrom, A.

“…Results from a series of experimental studies on the effect of assembly process conditions and design rules on solder joint quality for 0,5 and 0,65 mm pitch…”
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Low cost, high volume applications to drive high performance Si-on-Si MCM by Tai, K.L.

“…Summary form only given. As the design rule gap between VLSI and packaging technology widens, the mismatch of the electrical environments between on-chip and…”
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In-line, real-time nondestructive monitoring of Fe contamination for statistical process control (SPC) by surface photovoltage (SPV) by Lowell, J., Wenner, V., Thomas, J., Jastrzebski, L., Lagowski, J., Henley, W., DeBusk, D., Edelman, P., Nauka, C.

“…During high temperature operations, heavy metals will precipitate and form localized silicides at the silicon/oxide interface, which introduces weak spots that…”
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Application of Run by Run controller to the chemical-mechanical planarization process. I by Hu, A., ZiuRua Zhang, Sachs, E., Renteln, P.

“…The Run by Run (RbR) controller, combining the advantages both statistical process control (SPC) and automatic process control (APC) has been applied…”
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A research study to establish the need to implement cycle time reduction strategies for new package introduction by Goetsch, M.

“…The research is an ex-post facto design administered to a randomly sampled population of the assembly technology groups within one large semiconductor company…”
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Optimizing the wafer dicing process by Efrat, U.

“…Wafer dicing is one of the critical elements of the IC assembly process where improvements can make a major contribution to yield. Chipping (damage along the…”
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Microstructural evolution and mechanical properties of Sn-Bi based solders by Raeder, C.H., Felton, L.E., Knorr, D.B., Schmeelk, G.B., Lee, D.

“…An overview of issues relevant to reliability of Sn-Bi solder joints is presented. The effects of aging on the microstructure of Sn-Bi solder joints are…”
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Solder bump fabrication by electroplating for flip-chip applications by Yu, K.K., Tung, F.

“…A step-by-step description of a solder alloy bumping process for flip-chip application is discussed. Emphasis is placed on a 75-/spl mu/m high bump, as plated,…”
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Neural networks in manufacturing: A survey by Huang, S.H., Hong-Chao Zhang

“…Information about neural networks in manufacturing, which will provide some guidelines and references for the research and implementation is presented. The…”
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Wire bonding: Present and future trends by Chen, A.S., Nguyen, L.T., Burke, T.S., Belani, J.G.

“…Gold wire thermosonic bonding remains the primary means of electrically connecting the silicon chip to the outside world. To keep up with the increasing…”
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Reactive scheduling of a semiconductor testing facility by Perry, C.N., Uzsoy, R.

“…The authors describe an approach to scheduling complex job shops such as semiconductor testing operations which uses the global shop-floor information…”
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Solder replacement by Hvims, H.

“…The use of conductive adhesives as a replacement for solder on surface mount technology (SMT) printed circuit boards is discussed. A number of conductive…”
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Neural network-based modeling of the plasma-enhanced chemical vapor deposition of silicon dioxide by Han, S.S., Ceiler, M., Bidstrup, S.A., Kohl, P., May, G.

“…The properties of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide films are modeled using neural networks. This method is simple, extremely…”
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No clean mass reflow of large over molded plastic pad array carriers (OMPAC) by Lau, J., Miremadi, J., Gleason, J., Haven, R., Ottoboni, S., Mimura, S.

“…A no clean mass reflow process for 396-pin, 324-pin, and 225-pin over molded plastic pad array carriers (OMPAC) is presented. Emphasis is placed on the OMPAC…”
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"Hot" jobs, bane or boon by Trybula, W.J.

“…The manufacturing community reacts to crises, directives from upper management and late orders by issuing "hot orders". This method of operating increases the…”
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Thin film transfer process for low cost MCM's by Narayan, C., Purushothaman, S.

“…A highly flexible and cost competitive method to fabricate microelectronic packages that require thin film interconnections is described. The method involves…”
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Stress analysis and reliability of chip on board encapsulation technology by Sarbach, P., Guerin, L., Weber, A., Dutoit, M., Clot, P.

“…It is shown that polymerization and thermomechanical stresses are important in miniaturized chip on board (COB) modules. COB technology is reliable enough to…”
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Statistical methods in manufacturing by Wong, K.Y., Singh, V.P., Rustagi, J.S.

“…The application of design of experiments in manufacturing has been proposed and developed by Genichi Taguchi for quality improvement. An automated design of…”
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A work cell manufacturing system for VLSI fabrication by Ruey-Shan Gul, Slama, M., Griffin, R., Holman, K.

“…The concepts behind the next-generation work cell semiconductor manufacturing system capable of achieving competitive advantages in product quality, variety,…”
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The intelligent manufacturing systems initiative at Louisiana State University by Keys, L.K., Hirschfeld, R.A., Liao, T.W.

“…In the 1992 IEMT15S Proceedings Louisiana State University (LSU) presented the outlines for an initiative in mechatronics engineering. Progress, developments,…”
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