Search Results - "Proceedings Sixth Asian Test Symposium (ATS'97)"

New capabilities of OBIRCH method for fault localization and defect detection by Nikawa, K., Inoue, S.

“…We have improved the optical beam induced resistance change (OBIRCH) method so as to detect (1) a current path as small as 10-50 /spl mu/A from the rear side…”
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I/sub DDT/ testing by Yinghua Min, Zhuxing Zhao, Zhongcheng Li

“…The industry has accepted I/sub DDQ/ testing to detect CMOS IC defects. While I/sub DDT/ testing needs more research to be applicable in practice. However, it…”
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Embedded test and measurement critical for deep submicron technology by Agarwal, V.K.

“…The embedded test and measurement (ETM) technology has been known in the past by its various other names such as Built-In Test Equipment (BITE), Built-In Test…”
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Novel optical probing system for quarter-/spl mu/m VLSI circuits by Ozaki, K., Sekiguchi, H., Wakana, S., Goto, Y., Umehara, Y., Matsumoto, J.

“…An e-beam tester is widely used for the internal analysis of LSI circuits. However, its low waveform acquisition speed is a significant drawback for LSI…”
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A perturbation based fault modeling and simulation for mixed-signal circuits by Ben-Hamida, N., Saab, K., Marche, D., Kaminska, B.

“…The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due…”
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On fault injection approaches for fault tolerance of feedforward neural networks by Ito, T., Takanami, I.

“…To make a neural network fault-tolerant, Tan et al. proposed a learning algorithm which injects intentionally the snapping of a wire one by one into a network…”
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Accelerated test points selection method for scan-based BIST by Nakao, M., Hatayama, K., Higashi, I.

“…This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points…”
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Built-in self-test for multi-port RAMs by Yuejian Wu, Gupta, S.

“…Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed…”
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Test pattern and test configuration generation methodology for the logic of RAM-based FPGA by Renovell, M., Portal, J.M., Figueras, J., Zorian, Y.

“…The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by…”
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A XOR-tree based technique for constant testability of configurable FPGAs by Huang, W.K., Zhang, M.Y., Meyer, F.J., Lombardi, F.

“…This paper presents a novel approach for testing and diagnosing configurable field programmable gate arrays (FPGAs). The proposed approach is row-based and…”
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An algorithmic test generation method for crosstalk faults in synchronous sequential circuits by Itazaki, N., Matsumoto, Y., Kinoshita, K.

“…As VLSI circuits become high-speed and high-density, a crosstalk fault becomes an important problem. In a synchronous sequential circuit, since the crosstalk…”
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Integrated and automated design-for-testability implementation for cell-based ICs by Ono, T., Wakui, K., Hikima, H., Nakamura, Y., Yoshida, M.

“…This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along…”
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On chip weighted random patterns by Savir, J.

“…This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional…”
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Power supply current monitoring techniques for testing PLLs by Dalmia, M., Ivanov, A., Tabatabaei, S.

“…The effectiveness of current testing for digital IC's has led researchers to explore the possibility of extending this concept to testing analog blocks of…”
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On the capability of delay tests to detect bridges and opens by Chakravarty, S.

“…Recent empirical and simulation studies show that adding at-speed testing to the test suite helps in detecting defective ICs missed by slow-speed and I/sub…”
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Test compaction in a parallel access scan environment by Bhatia, S., Varma, P.

“…In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology,…”
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Fault diagnosis for static CMOS circuits by Wen Xiaoqing, Tamamoto, H., Saluja, K.K., Kinoshita, K.

“…This paper presents a new methodology for transistor leakage fault diagnosis using both I/sub DDQ/ and logic information. A method for handling intermediate…”
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On the adders with minimum tests by Kajihara, S., Sasao, T.

“…This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at-fault models. In the…”
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A method of generating tests for marginal delays and delay faults in combinational circuits by Takahashi, H., Matsunaga, T., Boateng, K.O., Takamatsu, Y.

“…In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD…”
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On acceleration of logic circuits optimization using implication relations by Ichihara, H., Kinoshita, K.

“…In logic synthesis the multi-level logic optimization methods using implication analysis has high performance but it needs a lot of computational time because…”
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