Search Results - "Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture"

Dynamic thermal management for high-performance microprocessors by Brooks, D., Martonosi, M.

“…With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity…”
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A delay model and speculative architecture for pipelined routers by Peh, L.-S., Dally, W.J.

“…This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary…”
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Dynamic branch prediction with perceptrons by Jimenez, D.A., Lin, C.

“…This paper presents a new method for branch prediction. The key idea is to use one of the simplest possible neural networks, the perceptron, as an alternative…”
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Reducing DRAM latencies with an integrated memory hierarchy design by Wei-Fen Lin, Reinhardt, S.K., Burger, D.

“…In this paper we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive,…”
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An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches by Yang, S., Powell, M.D., Falsafi, B., Roy, K., Vijaykumar, T.N.

“…Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold…”
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JETTY: filtering snoops for reduced energy consumption in SMP servers by Moshovos, A., Memik, G., Falsafi, B., Choudhary, A.

“…We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large…”
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Speculative data-driven multithreading by Roth, A., Sohi, G.S.

“…Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical…”
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Differential FCM: increasing value prediction accuracy by improving table usage efficiency by Goeman, B., Vandierendonck, H., de Bosschere, K.

“…Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when…”
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Self-tuned congestion control for multiprocessor networks by Thottethodi, M., Lebeck, A.R., Mukherjee, S.S.

“…One-track performance in tightly-coupled multiprocessors typically, degrades rapidly beyond network saturation. Consequently, designers must keep a network…”
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CARS: a new code generation framework for clustered ILP processors by Kailas, K., Ebcioglu, K., Agrawala, A.

“…Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes…”
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Dynamic prediction of critical path instructions by Tune, E., Dongning Liang, Tullsen, D.M., Calder, B.

“…Modern processors come close to executing as fast as role dependences allow. The particular dependences that constrain execution speed constitute the critical…”
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Branch history guided instruction prefetching by Srinivasan, V., Davidson, E.S., Tyson, G.S., Charney, M.J., Puzak, T.R.

“…Instruction cache misses stall the fetch stage of the processor pipeline and hence affect instruction supply to the processor. Instruction prefetching has been…”
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An architectural evaluation of Java TPC-W by Cain, H.W., Rajwar, R., Marden, M., Lipasti, M.H.

“…The use of the Java programming language for implementing server-side application logic is increasingly in popularity yet there is very little known about the…”
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Data-flow prescheduling for large instruction windows in out-of-order processors by Michaud, P., Seznec, A.

“…The performance of out-of-order processors increases with the instruction window size, In conventional processors, the effective instruction window cannot be…”
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A new scalable directory architecture for large-scale multiprocessors by Acacio, M.E., Gonzalez, J., Garcia, J.M., Duato, J.

“…The memory overhead introduced by directories constitutes a major hurdle in the scalability of cc-NUMA architectures, which makes the shared-memory paradigm…”
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Performance of hardware compressed main memory by Abali, B., Franke, H., Xiaowei Shen, Poff, D.E., Smith, T.B.

“…A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically…”
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Stack value file: custom microarchitecture for the stack by Lee, H.H.-S., Smelyanskiy, M., Newburn, C.J., Tyson, G.S.

“…As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed…”
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DRAM energy management using software and hardware directed power mode control by Delaluz, V., Kandemir, M., Vijaykrishnan, N., Sivasubramaniam, A., Irwin, M.J.

“…While there have been several studies and proposals for energy conservation for CPUs and peripherals, energy optimization techniques for selective operating…”
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A programmable co-processor for profiling by Zilles, C.B., Sohi, G.S.

“…Aggressive program optimization requires accurate profile information, but such accuracy requires many samples to be collected. We explore a novel profiling…”
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Towards virtually-addressed memory hierarchies by Xiaogang Qiu, Dubois, M.

“…Current cache hierarchies are indexed in parallel with a TLB but their tags are part of the physical address so that the memory hierarchy is physically…”
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