Search Results - "Proceedings 19th IEEE VLSI Test Symposium. VTS 2001"

Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression by Chandra, A., Chakrabarty, K.

“…We showed recently that Golomb codes can be used for efficiently compressing system-on-a-chip test data. We now present a new class of…”
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Reducing power dissipation during test using scan chain disable by Sankaralingam, R., Pouya, B., Touba, N.A.

“…A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the…”
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Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip by Iyengar, V., Chakrabarty, K.

“…Test scheduling is a major problem in system-on-a-chip (SOC) test automation. We present an integrated framework that addresses several important test…”
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A modified clock scheme for a low power BIST test pattern generator by Girard, P., Guiller, L., Landrault, C., Pravossoudovitch, S., Wunderlich, H.J.

“…In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during…”
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Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme by Jas, A., Krishna, C.V., Touba, N.A.

“…This paper presents a new test resource partitioning scheme that is a hybrid approach between external testing and BIST. It reduces tester storage requirements…”
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A self-test methodology for IP cores in bus-based programmable SoCs by Jing-Reng Huang, Iyer, M.K., Kwang-Ting Cheng

“…We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and…”
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A geometric-primitives-based compression scheme for testing systems-on-a-chip by El-Maleh, A., al Zahir, S., Khan, E.

“…The increasing complexity of systems-on-a-chip with the accompanied increase in their test data size has made the need for test data reduction imperative. In…”
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A method for measuring the cycle-to-cycle period jitter of high-frequency clock signals by Yamaguchi, T.J., Soma, M., Halter, D., Raina, R., Nissen, J., Ishida, M.

“…This paper introduces the extended /spl Delta//spl phi/ method for measuring cycle-to-cycle period jitter in PLL outputs. The theoretical basis for this method…”
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Flash memory disturbances: modeling and test by Mohammad, M.G., Saluja, K.K.

“…Nonvolatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the…”
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A low-cost adaptive ramp generator for analog BIST applications by Azais, F., Bernard, S., Bertrand, Y., Michel, X., Renovell, M.

“…This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive…”
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On improving the accuracy of multiple defect diagnosis by Shi-Yu Huang

“…Logic defect diagnosis locates the defect spots in a digital IC that fail testing. It is one of the critical steps during the process of manufacturing yield…”
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MINVDD testing for weak CMOS ICs by Chao-Wen Tseng, Chen, R., Nigh, P., McCluskey, E.J.

“…A weak chip is one that contains flaws-defects that do not interfere with correct circuit operation at normal conditions but may cause intermittent or…”
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An on-chip short-time interval measurement technique for testing high-speed communication links by Jiun-Lang Huang, Kwang-Ting Cheng

“…In this paper, we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specifications, e.g., the…”
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Electrically induced stimuli for MEMS self-test by Charlot, B., Mir, S., Parrain, F., Courtois, B.

“…A major problem for applying self-test techniques to MEMS is the multi-domain nature of the sensing parts that require special test equipment for stimuli…”
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Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories by Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu

“…We present two memory test algorithms for neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF…”
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An efficient methodology for generating optimal and uniform march tests by Al-Harbi, S.M., Gupta, S.K.

“…A large number of march tests that provide different fault coverages have been published and a few methodologies have been presented for automatically…”
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Automatic generation of diagnostic March tests by Niggemeyer, D., Rudnick, E.M.

“…A new approach to automatically generating diagnostic memory tests of linear order (/spl Oscr/(N)) is presented. The resulting March tests provide complete…”
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Test scheduling for minimal energy consumption under power constraints by Schuele, T., Stroele, A.P.

“…Power consumption has become a crucial concern in built-in self-test (BIST) due to the increased switching activity in the circuit under test. In this paper we…”
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Enabling embedded memory diagnosis via test response compression by Chen, J.T., Rajski, J., Khare, J., Kebichi, O., Maly, W.

“…This paper introduces a method that enables failure diagnosis of BISTed memories by compression of test responses. This method has been tested by simulation of…”
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An evaluation of pseudo random testing for detecting real defects by Chao-Wen Tseng, Mitra, S., Davidson, S., McCluskey, E.J.

“…Research has shown that single stuck-at fault (SSF) N-detect test sets are effective for detecting defects not modeled by the SSF model. Experimental results…”
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