Search Results - "Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)"

Generic global placement and floorplanning by Eisenmann, Hans, Johannes, Frank M.

“…We present a new force directed method for global placement. Besides the well-known wire length dependent forces we use additional forces to reduce cell…”
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Power considerations in the design of the Alpha 21264 microprocessor by Gowan, Michael K., Biro, Larry L., Jackson, Daniel B.

“…Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The…”
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Reducing power in high-performance microprocessors by Tiwari, Vivek, Singh, Deo, Rajgopal, Suresh, Mehta, Gaurav, Patel, Rakesh, Baez, Franklin

“…Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each…”
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MTCMOS hierarchical sizing based on mutual exclusive discharge patterns by Kao, James, Narendra, Siva, Chandrakasan, Anantha

“…Multi-threshold CMOS is a popular circuit style that will provide high performance and low power operation. Optimally sizing the gating sleep transistor to…”
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Validation with guided search of the state space by Yang, C. Han, Dill, David L.

“…In practice, model checkers are most useful when they find bugs, not when they prove a property. However, because large portions of the state space of the…”
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Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis by Krauter, Byron, Mehrotra, Sharad

“…It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]…”
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Automatic synthesis of interfaces between incompatible protocols by Passerone, Roberto, Rowson, James A., Sangiovanni-Vincentelli, Alberto

“…A t the system level, reusable Intellectual Property (or IP) blo cks can be represented abstractly as blocks that exchange messages. The concrete…”
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Buffer insertion for noise and delay optimization by Alpert, Charles J., Devgan, Anirudh, Quay, Stephen T.

“…Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack…”
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Global routing with crosstalk constraints by Zhou, Hai, Wong, D. F.

“…Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important…”
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Planning for performance by Otten, Ralph H. J. M., Brayton, Robert K.

“…A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a…”
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Finite state machine decomposition for low power by Monteiro, José C., Oliveira, Arlindo L.

“…Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe…”
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Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator by Hanono, Silvina, Devadas, Srinivas

“…The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures AVIV optimizes for…”
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Congestion driven quadratic placement by Parakh, Phiroze N., Brown, Richard B., Sakallah, Karem A.

“…This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe…”
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Figures of merit to characterize the importance of on-chip inductance by Ismail, Yehea I., Friedman, Eby G., Neves, Jose L.

“…A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law…”
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A decision procedure for bit-vector arithmetic by Barrett, Clark W., Dill, David L., Levitt, Jeremy R.

“…Bit-v ector theories with concatenation and extraction have been shown to be useful and important for hardware verification. We have implemented an extended…”
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Design methodologies for noise in digital integrated circuits by Shepard, Kenneth L.

“…In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity…”
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Functional vector generation for HDL models using linear programming and 3-satisfiability by Fallah, Farzan, Devadas, Srinivas, Keutzer, Kurt

“…Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The…”
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Code compression for embedded systems by Lekatsas, Haris, Wolf, Wayne

“…Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a…”
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Full-chip verification methods for DSM power distribution systems by Steele, Gregory, Overhauser, David, Rochel, Steffen, Hussain, Syed Zakir

“…Power distribution verification is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased…”
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A programming environment for the design of complex high speed ASICs by Schaumont, Patrick, Vernalde, Serge, Rijnders, Luc, Engels, Marc, Bolsens, Ivo

“…A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er…”
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