Search Results - "Proceedings 18th IEEE VLSI Test Symposium"

Test data compression for system-on-a-chip using Golomb codes by Chandra, A., Chakrabarty, K.

“…We present a new test data compression method and decompression architecture based on Golomb codes. The proposed method is especially suitable for encoding…”
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Extraction of peak-to-peak and RMS sinusoidal jitter using an analytic signal method by Yamaguchi, T.J., Soma, M., Ishida, M., Watanabe, T., Ohmi, T.

“…This paper proposes a new method based on analytic signal theory for extracting both instantaneous and RMS sinusoidal jitter from PLL output signals. The…”
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On testing the path delay faults of a microprocessor using its instruction set by Wei-Cheng Lai, Krstic, A., Kwang-Ting Cheng

“…This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a…”
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Cold delay defect screening by Chao-Wen Tseng, Mccluskey, E.J., Xiaoping Shao, Wu, D.M.

“…Delay defects can escape detection during the normal production test flow; particularly if they do not affect any of the long paths included in the test flow…”
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A comprehensive TDM comparator scheme for effective analysis of oscillation-based test by Roh, J., Abraham, J.A.

“…We propose a comprehensive built-in self-test (BIST) methodology for analog and mixed-signal circuits. A time-division multiplexing (TDM) comparator scheme was…”
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Validation of PowerPC/sup TM/ custom memories using symbolic simulation by Krishnamurthy, N., Martin, A.K., Abadir, M.S., Abraham, J.A.

“…This paper describes the use of Symbolic Trajectory Evaluation (STE), a modified form of symbolic simulation, to verify the equivalence between RTL and…”
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P1450.1: STIL for the simulation environment by Wohl, P., Biggs, N.

“…The Standard Test Interface Language (STIL IEEE-1450) was developed to transport patterns from the generation environment to testers. STIL was also shown to…”
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Crosstalk effect removal for analog measurement in analog test bus by Chauchin Su, Yue-Tsang Chen

“…A DSP based test methodology is proposed to remove the parasitic and crosstalk effects, the two major drawbacks when using the analog buses. Experiments, using…”
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A general BIST-amenable method of test generation for iterative logic arrays by Boateng, I.O., Takahashi, H., Takamatsu, Y.

“…In this work, we call a set of a constant number of test patterns that have a fixed fault coverage for any size of a given ILA a fixed coverage fixed size test…”
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Using arithmetic transform for verification of datapath circuits via error modeling by Radecka, K., Zilic, Z.

“…In this paper, we consider verification under error-model assumption. We exploit the algebraic properties of the arithmetic transforms that are used in compact…”
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Efficient diagnosis of single/double bridging faults with Delta Iddq probabilistic signatures and Viterbi algorithm by Thibeault, C.

“…This paper presents an efficient method to diagnose single and double bridging faults. This method is based on Delta Iddq probabilistic signatures, as well as…”
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At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor by Tendolkar, N., Molyneaux, R., Pyron, C., Raina, R.

“…In this paper we present the novel built-in delay fault test concepts incorporated into Motorola's MPC7400 PowerPC microprocessor that allow us to use a slow…”
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Word-voter: a new voter design for triple modular redundant systems by Mitra, S., McCluskey, E.J.

“…Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy…”
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A low-speed BIST framework for high-performance circuit testing by Speek, H., Kerkhoff, H.G., Shashaani, M., Sachdev, M.

“…Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test…”
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Invariance-based on-line test for RTL controller-datapath circuits by Makris, Y., Bayraktaroglu, I., Orailoglu, A.

“…We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation…”
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Hidden Markov and independence models with patterns for sequential BIST by Brehelin, L., Gascuel, O., Caraux, G., Girard, P., Landrault, C.

“…We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a…”
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Synthesis for arithmetic built-in self-test by Stroele, A.P.

“…Arithmetic built-in self-test (BIST) is a favorable test method for data paths that include adders, subtracters, and other arithmetic units. With these…”
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Space compaction of test responses for IP cores using orthogonal transmission functions by Seuring, M., Chakrabarty, K.

“…Space compaction of test responses provides parallel access to functional outputs and reduces delays on functional paths between cores. We present a new space…”
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Simulation-based test algorithm generation for random access memories by Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu

“…Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic…”
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Testability alternatives exploration through functional testing by Ferrandi, F., Ferrara, G., Fornara, G., Fummi, F., Sciuto, D.

“…The aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different…”
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