Search Results - "Proceedings 13th IEEE VLSI Test Symposium"

Redundancy removal and test generation for circuits with non-Boolean primitives by Chakradhar, S.T., Rothweiler, S.G., Agrawal, V.D.

“…Production VLSI circuits typically consist of primitives like tri-state buffers, bidirectional buffers and bus configurations that assume non-Boolean values…”
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Testability of floating gate defects in sequential circuits by Champac, V.H., Figueras, J.

“…The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential…”
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Transformed pseudo-random patterns for BIST by Touba, N.A., McCluskey, E.J.

“…This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR)…”
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Verification of transient response of linear analog circuits by Balivada, A., Hoskote, Y., Abraham, J.A.

“…With the introduction of complex analog designs the need to verify the circuit behavior completely and efficiently cannot be overemphasized. Recognizing the…”
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Reliability evaluation of combinational logic circuits by symbolic simulation by Bogliolo, A., Damiani, M., Olivo, P., Ricco, B.

“…This paper presents new algorithms for evaluating the reliability of fault-tolerant combinational logic circuits. In order to model the effects of multiple…”
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An optimized testable architecture for finite state machines by Ting-Yu Kuo, Chun-Yeh Liu, Saluja, K.K.

“…This paper presents a testable architecture for FSM synthesis. The transfer, synchronizing and distinguishing sequences are obtained simultaneously by adding…”
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Improving topological ATPG with symbolic techniques by Corno, F., Prinetto, P., Sonza Reorda, M., Glaser, U., Vierhaus, H.T.

“…This paper presents a new approach to Automatic Test Pattern Generation for sequential circuits. Traditional topological algorithms nowadays are able to deal…”
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An approach to dynamic power consumption current testing of CMOS ICs by Segura, J.A., Roca, M., Mateo, D., Rubio, A.

“…I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially…”
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Detectable perturbations: a paradigm for technology-specific multi-fault test generation by Zemva, A., Brglez, F.

“…This paper introduces the concept of detectable perturbations as a method to generate tests that can then cover any technology-specific faults such as multiple…”
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Resynthesis for sequential circuits designed with a specified initial state by Yotsuyanagi, H., Kajihara, S., Kinoshita, K.

“…This paper presents a retiming and redundancy removal method for a sequential circuit with a specified initial state so that the resynthesized circuit has a…”
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The concept of resistance interval: a new parametric model for realistic resistive bridging fault by Renovell, M., Huc, P., Bertrand, Y.

“…From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 /spl Omega/ to 500 /spl…”
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Diagnostic of path and gate delay faults in non-scan sequential circuits by Girard, P., Landrault, C., Pravossoudovitch, S., Rodriguez, B.

“…The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational…”
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Compact test sets for industrial circuits by Konijnenburg, M.H., van der Linden, J.T., van de Goor, A.J.

“…Industrial circuits contain, in addition to the binary logic elements [n] and, [n] or and [n] xor gates, other logic elements such as three-state elements,…”
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Structural constraints for circular self-test paths by Carletta, J., Papachristou, C.

“…Constraints on the structure of circular self-test paths in register transfer level (RTL) circuits with circular Built-In Self Test (BIST) features are…”
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Synthesis of locally exhaustive test pattern generators by Kemnitz, G.

“…Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new…”
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An approach for system tests design and its application by Shoukourian, S.K., Kostanian, A.G., Margarian, V.A., Ashour, A.A.

“…An approach for system test design is suggested and justified by the corresponding mathematical model. It is based on the representation of a testing process…”
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CURRENT: a test generation system for I/sub DDQ/ testing by Mahlstedt, U., Alt, J., Heinitz, M.

“…This paper presents an I/sub DDQ/ test generation system for scan-based circuits, called CURRENT. A library-based fault modeling strategy is used to specify a…”
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Self-test in a VCM driver chip by Sebaa, L., Gardner, N., Neidorff, R., Valley, R.

“…This paper describes a cost effective self-test mode in a complex mixed-signal device. The device under test (DUT) is a Voice-Coil Motor (VCM) H-bridge…”
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An experimental evaluation of the differential BICS for I/sub DDQ/ testing by Weber, W.W., Singh, A.D.

“…In this paper we present an experimental study on the effectiveness of I/sub DDQ/ testing using the differential built-in current sensor (BICS) circuit. Two…”
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A partial scan methodology for testing self-timed circuits by Khoche, A., Brunvand, E.

“…This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other…”
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