Search Results - "Preuber, Thomas B."

HyperLogLog Sketch Acceleration on FPGA by Kulkarni, Amit, Chiosa, Monica, Preusser, Thomas B., Kara, Kaan, Sidler, David, Alonso, Gustavo

“…Data sketches are a set of widely used approximated data summarizing techniques. Their fundamental property is sub-linear memory complexity on the input…”
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Using DSP Slices as Content-Addressable Update Queues by PreuBer, Thomas B, Chiosa, Monica, Weiss, Alexander, Alonso, Gustavo

“…Content-Addressable Memory (CAM) is a powerful abstraction for building memory caches, routing tables and hazard detection logic. Without a native CAM…”
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Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic by Blott, Michaela, PreuBer, Thomas B., Fraser, Nicholas, Gambardella, Giulio, O'Brien, Kenneth, Umuroglu, Yaman, Leeser, Miriam

“…Convolutional Neural Networks have dramatically improved in recent years, surpassing human accuracy on certain problems and performance exceeding that of…”
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Design Kernel Exploration Using QBF-Based Boolean Matching by PreuBer, Thomas B., Erxleben, Fredo

“…The synthesis and mapping of user designs to configurable hardware is typically performed by heuristics. These approaches analyze the decomposability of the…”
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PoC-align: An open-source alignment accelerator using FPGAs by Preuber, Thomas B., Knodel, Oliver, Spallek, Rainer G.

“…The mapping of reads, i.e. short DNA base pair strings, to large genome databases has become a critical operation for genetic analysis and diagnosis. The…”
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Analysis of a Fully-Scalable Digital Fractional Clock Divider by Preuber, Thomas B., Spallek, Rainer G.

“…It was previously shown [5] that the BRESENHAM algorithm [2] is well-suited for digital fractional clock generation. Specifically, it proved to be the optimal…”
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